All posts by vezhlys

VIA IDE and SATA controllers

2025-06-04 vezhlys

VIA has produced a wide range of chipsets, including southbridges and single-chip solutions, many of which feature their own versions of IDE and SATA controllers. In addition to these integrated solutions, VIA also released a few standalone SATA controllers. Since the introduction of SATA, VIA has experimented with various design approaches, often without a consistent pattern. This inconsistency is reflected in the varying levels of support across operating systems and within their drivers themselves.

Nevertheless, NetBSD offers fairly good support for most of these controllers through the viaide(4) driver. However, a few models exhibited incomplete or missing functionality, falling behind in certain areas compared to their support in other BSD variants or Linux.

In recent months, I’ve worked on improving support for several VIA controllers with previously incomplete functionality.

Adding VT8261 support

This began in January with the addition of support for the VT8261 integrated SATA/IDE controller, followed by a few minor refinements later on.

VT8261 is a southbridge paired with the VN1000 northbridge, a platform that saw very limited adoption. Some VIA development boards, such as the VT8591B, occasionally surface, especially following the dissolution of Centaur Technology. Another example is the Taiwan-only Acer VN1000-AM motherboard.

Functionally, VT8261 is similar to the earlier VT8251, offering four SATA ports over two channels (primary and secondary) and one PATA channel. PATA port is present on development boards but absent from the Acer board. The PCI IDs for the SATA and PATA controllers are distinct. The PATA controller uses the typical 0x0571 PCI ID, which means identification must rely on the ISA bus. The SATA controller uses PCI ID 0x9000 in IDE mode and 0x9040 in RAID mode. To support all four SATA ports, the SATA controller must be initialized using via_chip_map(), though there are some caveats I will explain later in the section on VT8251 support improvements.

Improved VX800 support

Next, I focused on improving support for the VIA VX800 chipset, which shares the same PCI ID with the CX700, CX700M, CX700M2, and VX700 chipsets. All of these are single-chip solutions that integrate both the northbridge and southbridge into a single package, referred to by VIA as a Media System Processor (MSP).

This chipset differs from others in that it supports two SATA ports on one channel and one PATA port on the second channel, both sharing the same PCI ID (0x5324 in IDE mode, 0x0581 in RAID mode). The initial implementation reused initialization code from the VT6421(A/L), which incidentally worked for the SATA ports, but failed to detect PATA drives. It also produced errors, as this chipset doesn’t use BAR(5) to map SATA registers in comparison to VT6421 and few other older VIA SATA controllers.

Getting this chipset fully functional took significant effort. I experimented with several more complex approaches that handled SATA and PATA channel initialization separately. However, the final solution was suggested to me to simply use via_chip_map() again. For this controller, it turned out to work right out of the box for both channels.

VIA V-RAID improvements

Most VIA SATA controllers support software RAID, known as VIA V-RAID, and typically include management firmware. This mode is enabled by switching the controller to RAID mode in the BIOS. Almost all VIA SATA controllers support this feature, provided the BIOS includes a RAID option. On add-in cards like the VT6421, RAID mode is always active if a firmware chip is installed. The IDE-only VT6410 controller also supports V-RAID.

NetBSD provides support for VIA V-RAID through the ataraid(4) driver. However, V-RAID is rarely used today, as RAIDframe is the preferred method for creating software RAID in NetBSD. Unlike vendor-specific implementations, RAIDframe is controller-independent. Still, NetBSD continues to provide both options, and ataraid(4) remains compatible with VIA’s implementation.

While working on VX800, I began testing V-RAID and quickly encountered an issue: the driver was indexing disks by channel. On controllers that have two disks per channel (CX700/VX700/VX800/VT8251/VT8261/VX900/VX11/VT6410), this led to overwriting one disk entry and triggered a separate ataraid(4) bug that caused a crash when RAID disks were missing.

To resolve this, I modified the code to use the disk index stored in the V-RAID metadata instead. This ensures consistent indexing that matches what the firmware assigns. As a result, I also fixed the crash issue, improving error handling for missing RAID disks, which works for other vendor RAID formats as well.

Finally, I added the check for the VT6421 controller’s RAID capability, enabling ataraid(4) on this hardware.

Further improvements, such as support for spare disks, may be needed in the future, but these are currently a low priority.

VT8237S UDMA mode fix

The VT8237S is another classic VIA southbridge, featuring two SATA ports, each on its own channel, and two PATA ports across separate channels. SATA functionality is properly supported in both IDE and RAID modes, using PCI IDs 0x5372 and 0x7372 respectively.

However, the PATA controller shares the common 0x0571 PCI ID, so identifying its UDMA capability requires checking the ISA bus. By default, NetBSD disables UDMA if the ISA bus is not recognized. The fix was straightforward: adding the VT8237S to the identification list, which allows PATA drives to operate at full speed. This fix is likely needed for OpenBSD as well.

VT6415 IDE support implementation

The VIA VT6415 controller is quite different from other VIA storage controllers. It is a single-channel (one-port) PCIe IDE controller. A related variant, the VT6330, combines this controller with a FireWire interface. It was used in some motherboards to provide a legacy PATA interface, as well as in at least one known standalone PCI card.

Unlike other VIA controllers, the VT6415 uses an undocumented and non-standard register layout, which made support more complex than it might initially seem. It required introducing a new flag to handle single-channel operation, since all other VIA controllers have two channels, as well as another flag to simulate the channel enable bit, whose location is still unknown.

While working on VT6415 support, I also implemented several general improvements, including a more accurate RAID capability check and better controller identification logic.

Bringing up RAID Mode on VX900

The VIA VX900 is one of the latest VIA Media System Processors (MSPs), followed only by the VX11, not counting the Zhaoxin derivatives and the unreleased Centaur CNS platform. Both the VX900 and VX11 appear to use the same PCI IDs for their SATA controllers.

Unlike earlier chipsets, the VX900 supports only two SATA ports, each on its own channel, and has no PATA support. IDE mode (PCI ID 0x9001) has been supported in NetBSD for some time. However, very few motherboards support RAID mode (PCI ID 0x9041). One exception is the ECS VX900-I , which I managed to track down.

The RAID firmware on this board differs from earlier implementations in that it does not include an option to configure RAID volumes. Instead, it requires separate software, likely Windows-based. However, it does detect and boot from preconfigured arrays correctly.

Adding support for this controller was straightforward, but having access to real hardware allowed me to confirm the PCI ID and verify RAID functionality directly.

VT8251 IDE/RAID mode functionality

I saved work on the VT8251 southbridge for last, and with good reason. Alongside the rare VT8261, it is one of only two VIA southbridges that support four SATA ports across two channels. In addition, it provides two PATA ports, comes in two revisions (CD and CE) with subtle behavioral differences, and operates in three modes: IDE, RAID, and AHCI.

The VT8251 was likely the final VIA southbridge to be paired not only with VIA platforms, but also with Intel and AMD systems. As a result, it saw moderate adoption in early AMD K8 and Intel Core 2 Duo motherboards, and was also used in a few VIA CPU-based boards, most notably the VIA EPIA-SN.

From old bug report, I already knew there were issues in IDE and RAID modes. AHCI mode appears to work reliably, but it is handled by a separate driver, ahcisata(4). I initially tested the controller on an ASUS A8V-VM (Socket 939, AMD Athlon64), which uses the older CD revision. This board reported PCI ID 0x3349 in all three modes (IDE, RAID, and AHCI), which surprised me at first since other IDs had been reported elsewhere.

Further investigation revealed that the newer CE revision uses different PCI IDs for each mode: 0x5287 for IDE, 0x6287 for AHCI, and 0x3349 (same as CD) for RAID mode. The PATA controller still uses the standard 0x0571 PCI ID. However, some buggy BIOSes appear to misassign 0x5287 to the PATA controller. If such systems are still in use, handling them properly would be difficult, although likely possible by checking whether the controller is attached as function 1.

I later found an MSI MS-7318 motherboard that uses the CE revision, and in this case, the board was equipped with even less common VT8251L-marked southbridge. This allowed me to test both hardware revisions directly.

Initial testing confirmed that the previously reported issues were still present. Only the first SATA port was detecting a hard disk. BAR(5) was using a “32-bit non-prefetchable memory” type instead of an I/O address, which caused failures when mapping the controller registers. If no drive was attached to the first port, a bogus device would appear. Connecting drives to the other ports could lead to timeouts or other errors.

The first attempt to simply use the via_chip_map() function brought partial improvement. The bogus device no longer appeared, and most ports were able to detect drives. However, new issues were observed. For example, connecting certain drives to the fourth port could cause timeouts. Using any port on the second channel (ports 3 or 4) would cause PATA drives to disappear, regardless of which channel they were on. These behaviors occurred consistently across both the CD and CE revisions.

Interestingly, the same hardware worked without issue under OpenBSD, which uses a very similar driver. At one point I considered committing the partial fix, since it slightly improved the situation. However, after further investigation, I identified the root cause. Some registers are shared between the SATA and IDE controllers, and NetBSD’s ATA channel setup code was writing to an offset that only made sense for the PATA controller. On the SATA controller, that offset had a different function, which led to these problems.

To fix this, I switched SATA controller initialization to use the dedicated SATA channel setup path. This resolved the issues for VT8251 and also applies to VT8261, which is affected in the same way. I included VX900 as well, since it could potentially be impacted even though it does not include a PATA controller.

With these changes, all drives could finally be detected and used reliably in both IDE and RAID modes.

For AHCI support, the CE revision needed to be added to the quirk list. The CD revision had also been misidentified as a VT8237R in AHCI mode, so I corrected the name to reflect its actual configuration.

VT6410 add-in cards and missing enable bits

The VIA VT6410 is an older IDE-only controller, supporting two PATA ports (up to four drives total). It is the only VIA PATA controller known to support RAID functionality. While it was sometimes integrated directly onto motherboards, standalone PCI cards based on this controller were also available. Onboard versions typically included BIOS support with RAID firmware, while add-in cards were often ROM-less, even though they still reported themselves as RAID-capable.

During work on the VT6415, I looked into OpenBSD and Linux implementations, which treat both VT6410 and VT6415 as lacking functional channel enable bits at register offset 0x40. To handle this, those drivers simulate the presence of the bits to ensure proper configuration. However, the underlying reasons for the missing bits differ between the two controllers.

The VT6415 is a single-channel PCIe IDE controller that appears to use a different and undocumented register layout compared to most other VIA controllers. It lacks the standard enable bits, or they may be located elsewhere. Fortunately, the channel is enabled by default, and simulating the bits is enough to convince the driver to proceed with configuration.

The VT6410, on the other hand, uses a more traditional register structure. Although documentation is unavailable, comparing PCI register dumps reveals that it does include the enable bits in the expected location. However, on add-in PCI cards, these bits are set to 00, effectively disabling the channels. On soldered versions found on motherboards, they are set correctly to 11.

Simply simulating the bits, as done for VT6415, gives the appearance that the channels are being configured. In reality, however, no drives are attached because the hardware remains disabled. The correct fix was to explicitly set the enable bits to 11, which properly activates the channels and allows drives to be detected and initialized.

Final notes

This concludes my major work on VIA IDE/SATA controllers for the time being. It has been an interesting and rewarding personal experience. I believe these improvements bring NetBSD on par with other major operating systems and even fix a few issues that others have missed so far.

There are still a few things left to improve, such as setting proper link speed for SATA ports (at least as I currently understand it), testing resume support, and refining certain RAID features. However, given the largely obsolete nature of this hardware today, these tasks may be of lower priority. That said, at least the basic support is now in place.

Most of the changes have been applied or will be applied to the NetBSD 10 and 9 branches. They should be available in the next point releases, or can be tested now using the latest branch builds from https://nycdn.netbsd.org/ for those who are impatient.

I did not test the VT8237A at all during this work, as I do not have the hardware. However, it is quite similar to other VT8237 variants (R and S), so I do not expect any surprises in functionality. It should work as expected.

The VX855 chipset was also untested. I expect it to work, but it differs from other VIA solutions by having two PATA channels, with one sometimes repurposed for a SATA port via an IDE–SATA bridge.

One more major task on my list is adding VT6421A controller support on cardbus(4) someday. This is a bit more complex to implement correctly, so, as usual, no promises on when or if that will happen.

I would like to give special credit to the https://dmesgd.nycbug.org/, https://linux-hardware.org/ and https://bsd-hardware.info/ projects, which were extremely helpful in gathering information on hardware I do not personally own.

I encourage everyone to check these sites and contribute their hardware data if possible. It really makes a difference. I also plan to contribute more actively myself.

It would be great to see a community project focused on collecting PCI register dumps. Just an idea for anyone interested. This kind of resource would offer valuable insight and could reduce the need to obtain physical hardware for testing.

Another project worth mentioning is https://theretroweb.com/, which has been very useful for identifying motherboards and cards using specific hardware and locating its documentation. For datasheets and legacy documentation, https://bitsavers.trailing-edge.com/ has been absolutely essential, particularly for VIA-related material. Finally, https://pci-ids.ucw.cz/ is also an important resource for documenting and easily looking up PCI IDs. Please consider supporting these projects and contributing your own hardware where possible.

Of course, special thanks go to the NetBSD project and its developers for reviewing my code and providing valuable advice.

NetBSD

NetBSD 10.1 release announced!

2024-12-21 vezhlys

The NetBSD 10.1 release has just been announced by the project team, marking the first feature release of the latest netbsd-10 branch. Key improvements and fixes are highlighted in the release announcement, while a more comprehensive list of changes compared to the 10.0 release can be found in the CHANGES-10.1 file. The release is available for download via the CDN service or the other project’s mirrors.

Users of earlier NetBSD releases are strongly encouraged to update to this version.

Full dmesg below:

NetBSD 10.1 on Epyc 4464P/ASUS PROART B650-CREATOR/Radeon RX5700XT

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013,
2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023,
2024
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.

NetBSD 10.1 (GENERIC_AMDGPU) #0: Fri Dec 20 10:53:52 EET 2024
andriusv@agraphic-pc:/home/andriusv/obj/sys/arch/amd64/compile/GENERIC_AMDGPU
total memory = 65240 MB
avail memory = 63080 MB
timecounter: Timecounters tick every 10.000 msec
Kernelized RAIDframe activated
timecounter: Timecounter “i8254” frequency 1193182 Hz quality 100
efi: systbl at pa 79e7e018
mainbus0 (root)
ACPI: RSDP 0x0000000074A01014 000024 (v02 ALASKA)
ACPI: XSDT 0x0000000074A00728 0000DC (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: FACP 0x00000000749F6000 000114 (v06 ALASKA A M I 01072009 AMI 00010013)
ACPI: DSDT 0x00000000749D6000 00EA2E (v162 ALASKA A M I 01072009 INTL 20230331)
ACPI: FACS 0x00000000769E8000 000040
ACPI: SSDT 0x00000000749F8000 007F64 (v02 AMD Splinter 00000002 MSFT 04000000)
ACPI: SSDT 0x00000000749F7000 000309 (v02 ALASKA CPUSSDT 01072009 AMI 01072009)
ACPI: FIDT 0x00000000749EB000 00009C (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: MCFG 0x00000000749E9000 00003C (v01 ALASKA A M I 01072009 MSFT 00010013)
ACPI: HPET 0x00000000749E8000 000038 (v01 ALASKA A M I 01072009 AMI 00000005)
ACPI: WDRT 0x00000000749E7000 000047 (v01 ALASKA A M I 01072009 AMI 00000005)
ACPI: FPDT 0x00000000749E5000 000044 (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: BGRT 0x00000000749F5000 000038 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: WPBT 0x00000000749F3000 000040 (v01 ALASKA A M I 00000001 ASUS 00000001)
ACPI: TPM2 0x00000000749F2000 00004C (v04 ALASKA A M I 00000001 AMI 00000000)
ACPI: SSDT 0x00000000748F1000 0074CE (v02 AMD AMD CPU 00000001 AMD 00000001)
ACPI: SSDT 0x00000000749F1000 0008BA (v02 AMD CPMDFDG2 00000001 INTL 20230331)
ACPI: SSDT 0x00000000749F0000 000788 (v02 AMD CPMDFIG5 00000001 INTL 20230331)
ACPI: SSDT 0x00000000748E7000 009A4C (v02 AMD CPMCMN 00000001 INTL 20230331)
ACPI: SSDT 0x00000000749ED000 0023CE (v02 AMD AOD 00000001 INTL 20230331)
ACPI: WSMT 0x00000000749EC000 000028 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: APIC 0x00000000748E6000 00015E (v05 ALASKA A M I 01072009 AMI 00010013)
ACPI: IVRS 0x00000000748E5000 0000C8 (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: SSDT 0x00000000748E4000 000500 (v02 AMD MEMTOOL0 00000002 INTL 20230331)
ACPI: SSDT 0x00000000748E3000 00097F (v02 AMD CPMMSOSC 00000001 INTL 20230331)
ACPI: SSDT 0x00000000748E2000 00047C (v02 AMD AMDWOV 00000001 INTL 20230331)
ACPI: SSDT 0x00000000748E1000 00044E (v02 AMD AmdTable 00000001 INTL 20230331)
ACPI: 12 ACPI AML tables successfully acquired and loaded
ioapic0 at mainbus0 apid 32: pa 0xfec00000, version 0x21, 24 pins
ioapic1 at mainbus0 apid 33: pa 0xfec01000, version 0x21, 32 pins
cpu0 at mainbus0 apid 0
cpu0: Use mfence to serialize rdtsc
cpu0: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu0: node 0, package 0, core 0, smt 0
cpu0: searching errata for cpu revision 0x00a60f12
cpu1 at mainbus0 apid 2
cpu1: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu1: node 0, package 0, core 1, smt 0
cpu2 at mainbus0 apid 4
cpu2: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu2: node 0, package 0, core 2, smt 0
cpu3 at mainbus0 apid 6
cpu3: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu3: node 0, package 0, core 3, smt 0
cpu4 at mainbus0 apid 8
cpu4: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu4: node 0, package 0, core 4, smt 0
cpu5 at mainbus0 apid 10
cpu5: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu5: node 0, package 0, core 5, smt 0
cpu6 at mainbus0 apid 16
cpu6: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu6: node 0, package 0, core 8, smt 0
cpu7 at mainbus0 apid 18
cpu7: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu7: node 0, package 0, core 9, smt 0
cpu8 at mainbus0 apid 20
cpu8: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu8: node 0, package 0, core 10, smt 0
cpu9 at mainbus0 apid 22
cpu9: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu9: node 0, package 0, core 11, smt 0
cpu10 at mainbus0 apid 24
cpu10: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu10: node 0, package 0, core 12, smt 0
cpu11 at mainbus0 apid 26
cpu11: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu11: node 0, package 0, core 13, smt 0
cpu12 at mainbus0 apid 1
cpu12: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu12: node 0, package 0, core 0, smt 1
cpu13 at mainbus0 apid 3
cpu13: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu13: node 0, package 0, core 1, smt 1
cpu14 at mainbus0 apid 5
cpu14: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu14: node 0, package 0, core 2, smt 1
cpu15 at mainbus0 apid 7
cpu15: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu15: node 0, package 0, core 3, smt 1
cpu16 at mainbus0 apid 9
cpu16: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu16: node 0, package 0, core 4, smt 1
cpu17 at mainbus0 apid 11
cpu17: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu17: node 0, package 0, core 5, smt 1
cpu18 at mainbus0 apid 17
cpu18: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu18: node 0, package 0, core 8, smt 1
cpu19 at mainbus0 apid 19
cpu19: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu19: node 0, package 0, core 9, smt 1
cpu20 at mainbus0 apid 21
cpu20: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu20: node 0, package 0, core 10, smt 1
cpu21 at mainbus0 apid 23
cpu21: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu21: node 0, package 0, core 11, smt 1
cpu22 at mainbus0 apid 25
cpu22: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu22: node 0, package 0, core 12, smt 1
cpu23 at mainbus0 apid 27
cpu23: AMD EPYC 4464P 12-Core Processor , id 0xa60f12
cpu23: node 0, package 0, core 13, smt 1
acpi0 at mainbus0: Intel ACPICA 20221020
acpi0: X/RSDT: OemId <ALASKA, A M I ,01072009>, AslId <AMI ,01000013>
acpi0: autoconfiguration error: invalid PCI address for D004
acpi0: autoconfiguration error: invalid PCI address for D005
acpi0: autoconfiguration error: invalid PCI address for D010
acpi0: MCFG: segment 0, bus 0-255, address 0x00000000e0000000
acpi0: SCI interrupting at int 9
acpi0: fixed power button present
timecounter: Timecounter “ACPI-Fast” frequency 3579545 Hz quality 1000
hpet0 at acpi0: high precision event timer (mem 0xfed00000-0xfed00400)
timecounter: Timecounter “hpet0” frequency 14318180 Hz quality 2000
AMDN (PNP0C01) at acpi0 not configured
attimer1 at acpi0 (TMR, PNP0100): io 0x40-0x43 irq 0
pcppi1 at acpi0 (SPKR, PNP0800): io 0x61
spkr0 at pcppi1: PC Speaker
wsbell at spkr0 not configured
midi0 at pcppi1: PC speaker
sysbeep0 at pcppi1
com0 at acpi0 (UAR1, PNP0501-0): io 0x3f8-0x3ff irq 4
com0: ns16550a, 16-byte FIFO
acpibut0 at acpi0 (PWRB, PNP0C0C-170): ACPI Power Button
TPM (MSFT0101) at acpi0 not configured
acpiwmi0 at acpi0 (ATKD, PNP0C14-ATK): ACPI WMI Interface
acpiwmibus at acpiwmi0 not configured
ASUP (ASUS2018) at acpi0 not configured
GPIO (AMDI0030) at acpi0 not configured
PPKG (AMDI0052) at acpi0 not configured
dwiic0 at acpi0 (I2CA, AMDI0010-0): mem 0xfedc2000-0xfedc2fff irq 10
resource type 0x11 ignored
resource type 0x11 ignored
iic0 at dwiic0: I2C bus
ihidev0 at iic0 addr 0x4eihidev0: autoconfiguration error: failed to get HidDescriptorAddress: AE_NOT_FOUND
PTIO (AMDIF031) at acpi0 not configured
acpiwmi1 at acpi0 (AWW0, PNP0C14-AWW): ACPI WMI Interface
acpiwmibus at acpiwmi1 not configured
acpiwmi2 at acpi0 (RMTW, PNP0C14-AsusMbSwInterface): ACPI WMI Interface
wmieeepc0 at acpiwmi2: Asus Eee PC WMI mappings
acpiwmi3 at acpi0 (AOD, PNP0C14-AOD): ACPI WMI Interface
acpiwmibus at acpiwmi3 not configured
acpiwdrt0 at acpi0: mem 0xfeb00000,0xfeb00004
acpiwdrt0: watchdog interval 1-1023 sec.
ACPI: Enabled 2 GPEs in block 00 to 1F
attimer1: attached to pcppi1
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
amdsmn0 at pci0 dev 0 function 0: AMD System Management Network
amdzentemp0 at amdsmn0: AMD CPU Temperature Sensors (Family19h)
AMD 19h/6xh IOMMU (IOMMU system) at pci0 dev 0 function 2 not configured
pchb0 at pci0 dev 1 function 0: AMD 19h/6xh PCIe Dummy Host Bridge (rev. 0x00)
ppb0 at pci0 dev 1 function 1: AMD 19h/6xh PCIe GPP Bridge (rev. 0x00)
ppb0: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x16 @ 16.0GT/s
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
ppb1 at pci1 dev 0 function 0: ATI Technologies product 1478 (rev. 0xc1)
ppb1: PCI Express capability version 2 <Upstream Port of PCI-E Switch>
pci2 at ppb1 bus 2
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
ppb2 at pci2 dev 0 function 0: ATI Technologies product 1479 (rev. 0x00)
ppb2: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x16 @ 16.0GT/s
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled, rd/line, wr/inv ok
amdgpu0 at pci3 dev 0 function 0: ATI Technologies Radeon RX 5600 OEM/5600 XT / 5700/5700 XT (rev. 0xc1)
hdaudio0 at pci3 dev 0 function 1: HD Audio Controller
hdaudio0: interrupting at msi0 vec 0
hdaudio0: HDA ver. 1.0, OSS 6, ISS 0, BSS 0, SDO 1, 64-bit
hdafg0 at hdaudio0: ATI R6xx HDMI
hdafg0: HDMI00 2ch: Digital Out [Jack]
hdafg0: HDMI01 2ch: Digital Out [Jack]
hdafg0: HDMI02 2ch: Digital Out [Jack]
hdafg0: HDMI03 2ch: Digital Out [Jack]
hdafg0: HDMI04 2ch: Digital Out [Jack]
hdafg0: HDMI05 2ch: Digital Out [Jack]
hdafg0: 2ch/0ch 32000Hz 44100Hz 48000Hz PCM16 AC3
audio0 at hdafg0: playback
audio0: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
spkr1 at audio0: PC Speaker (synthesized)
wsbell at spkr1 not configured
ppb3 at pci0 dev 1 function 2: AMD 19h/6xh PCIe GPP Bridge (rev. 0x00)
ppb3: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x4 @ 32.0GT/s
ppb3: link is x4 @ 8.0GT/s
pci4 at ppb3 bus 4
pci4: i/o space, memory space enabled, rd/line, wr/inv ok
nvme0 at pci4 dev 0 function 0: Western Digital (SanDisk) product 5019 (rev. 0x01)
nvme0: NVMe 1.4
nvme0: for admin queue interrupting at msix1 vec 0
nvme0: WDC WDS100T2B0C-00PXH0, firmware 233010WD, serial 21281W452002
nvme0: for io queue 1 interrupting at msix1 vec 1 affinity to cpu0
nvme0: for io queue 2 interrupting at msix1 vec 2 affinity to cpu1
nvme0: for io queue 3 interrupting at msix1 vec 3 affinity to cpu2
nvme0: for io queue 4 interrupting at msix1 vec 4 affinity to cpu3
nvme0: for io queue 5 interrupting at msix1 vec 5 affinity to cpu4
nvme0: for io queue 6 interrupting at msix1 vec 6 affinity to cpu5
nvme0: for io queue 7 interrupting at msix1 vec 7 affinity to cpu6
nvme0: for io queue 8 interrupting at msix1 vec 8 affinity to cpu7
nvme0: for io queue 9 interrupting at msix1 vec 9 affinity to cpu8
nvme0: for io queue 10 interrupting at msix1 vec 10 affinity to cpu9
nvme0: for io queue 11 interrupting at msix1 vec 11 affinity to cpu10
nvme0: for io queue 12 interrupting at msix1 vec 12 affinity to cpu11
nvme0: for io queue 13 interrupting at msix1 vec 13 affinity to cpu12
nvme0: for io queue 14 interrupting at msix1 vec 14 affinity to cpu13
nvme0: for io queue 15 interrupting at msix1 vec 15 affinity to cpu14
nvme0: for io queue 16 interrupting at msix1 vec 16 affinity to cpu15
ld0 at nvme0 nsid 1
ld0: 931 GB, 121601 cyl, 255 head, 63 sec, 512 bytes/sect x 1953525168 sectors
pchb1 at pci0 dev 2 function 0: AMD 19h/6xh PCIe Dummy Host Bridge (rev. 0x00)
ppb4 at pci0 dev 2 function 1: AMD 19h/6xh PCIe GPP Bridge (rev. 0x00)
ppb4: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x4 @ 32.0GT/s
ppb4: link is x4 @ 16.0GT/s
pci5 at ppb4 bus 5
pci5: i/o space, memory space enabled, rd/line, wr/inv ok
ppb5 at pci5 dev 0 function 0: AMD product 43f4 (rev. 0x01)
ppb5: PCI Express capability version 2 <Upstream Port of PCI-E Switch>
pci6 at ppb5 bus 6
pci6: i/o space, memory space enabled, rd/line, wr/inv ok
ppb6 at pci6 dev 0 function 0: AMD product 43f5 (rev. 0x01)
ppb6: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x4 @ 16.0GT/s
ppb6: link is x4 @ 8.0GT/s
pci7 at ppb6 bus 7
pci7: i/o space, memory space enabled, rd/line, wr/inv ok
aq0 at pci7 dev 0 function 0: Aquantia AQC100 10 Gigabit Network Adapter (rev. 0x02)
aq0: Atlantic revision B1, F/W version 3.1.58
aq0: fw2x> F/W capabilities=0x63c0001900007f20<PAUSE,ASYMMETRIC-PAUSE,LINK-DROP,SLEEP-PROXY,WOL,MAC-STOP,WOL-TIMER,STATISTICS>
aq0: Etheraddr: [_MAC_XXXXXXXXXX]
ppb7 at pci6 dev 8 function 0: AMD product 43f5 (rev. 0x01)
ppb7: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x1 @ 16.0GT/s
pci8 at ppb7 bus 8
pci8: i/o space, memory space enabled, rd/line, wr/inv ok
ppb8 at pci6 dev 9 function 0: AMD product 43f5 (rev. 0x01)
ppb8: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x1 @ 16.0GT/s
ppb8: link is x1 @ 2.5GT/s
pci9 at ppb8 bus 9
pci9: i/o space, memory space enabled, rd/line, wr/inv ok
re0 at pci9 dev 0 function 0: RealTek 8168/8111 PCIe Gigabit Ethernet (rev. 0x15)
re0: interrupting at msix3 vec 0
re0: RTL8168H/8111H (0x5400)
re0: Ethernet address [_MAC_XXXXXXXXXX]
re0: using 256 tx descriptors
rgephy0 at re0 phy 7: RTL8251 1000BASE-T media interface, rev. 0
rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto
ppb9 at pci6 dev 10 function 0: AMD product 43f5 (rev. 0x01)
ppb9: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x1 @ 16.0GT/s
ppb9: link is x1 @ 5.0GT/s
pci10 at ppb9 bus 10
pci10: i/o space, memory space enabled, rd/line, wr/inv ok
rge0 at pci10 dev 0 function 0: Realtek Semiconductor 8125 10/100/1G/2.5G Ethernet (rev. 0x05)
rge0: interrupting at msix4 vec 0
rge0: Ethernet address [_MAC_XXXXXXXXXX]
ppb10 at pci6 dev 11 function 0: AMD product 43f5 (rev. 0x01)
ppb10: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x1 @ 16.0GT/s
pci11 at ppb10 bus 11
pci11: i/o space, memory space enabled, rd/line, wr/inv ok
ppb11 at pci6 dev 12 function 0: AMD product 43f5 (rev. 0x01)
ppb11: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x1 @ 2.5GT/s
pci12 at ppb11 bus 12
pci12: i/o space, memory space enabled, rd/line, wr/inv ok
xhci0 at pci12 dev 0 function 0: AMD product 43f7 (rev. 0x01)
xhci0: 64-bit DMA
xhci0: interrupting at msix5 vec 0
xhci0: Unknown revision (32). Set to 3.1.
xhci0: xHCI version 1.10
usb0 at xhci0: USB revision 3.1
usb1 at xhci0: USB revision 2.0
ppb12 at pci6 dev 13 function 0: AMD product 43f5 (rev. 0x01)
ppb12: PCI Express capability version 2 <Downstream Port of PCI-E Switch> x1 @ 2.5GT/s
pci13 at ppb12 bus 13
pci13: i/o space, memory space enabled, rd/line, wr/inv ok
ahcisata0 at pci13 dev 0 function 0: AMD product 43f6 (rev. 0x01)
ahcisata0: 64-bit DMA
ahcisata0: AHCI revision 1.31, 6 ports, 32 slots, CAP 0xef36ff25<SXS,PSC,SSC,PMD,SPM,SAM,ISS=0x3=Gen3,SCLO,SAL,SALP,SSS,SSNTF,SNCQ,S64A>
ahcisata0: interrupting at msi6 vec 0
atabus0 at ahcisata0 channel 0
atabus1 at ahcisata0 channel 1
atabus2 at ahcisata0 channel 2
atabus3 at ahcisata0 channel 3
pchb2 at pci0 dev 3 function 0: AMD 19h/6xh PCIe Dummy Host Bridge (rev. 0x00)
pchb3 at pci0 dev 4 function 0: AMD 19h/6xh PCIe Dummy Host Bridge (rev. 0x00)
pchb4 at pci0 dev 8 function 0: AMD 19h/6xh PCIe Dummy Host Bridge (rev. 0x00)
ppb13 at pci0 dev 8 function 1: AMD 19h/6xh Internal PCIe GPP Bridge (rev. 0x00)
ppb13: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x16 @ 16.0GT/s
pci14 at ppb13 bus 14
pci14: i/o space, memory space enabled, rd/line, wr/inv ok
AMD 19h/6xh PCIe Dummy Function (non-essential instrumentation, subclass 0x00, revision 0xc4) at pci14 dev 0 function 0 not configured
amdccp0 at pci14 dev 0 function 2: AMD Cryptographic Coprocessor
xhci1 at pci14 dev 0 function 3: AMD 19h/6xh USB 3.1 xHCI (rev. 0x00)
xhci1: 64-bit DMA
xhci1: interrupting at msix7 vec 0
xhci1: xHCI version 1.20
usb2 at xhci1: USB revision 3.1
usb3 at xhci1: USB revision 2.0
xhci2 at pci14 dev 0 function 4: AMD 19h/6xh USB 3.1 xHCI (rev. 0x00)
xhci2: 64-bit DMA
xhci2: interrupting at msix8 vec 0
xhci2: xHCI version 1.20
usb4 at xhci2: USB revision 3.1
usb5 at xhci2: USB revision 2.0
hdaudio1 at pci14 dev 0 function 6: HD Audio Controller
hdaudio1: interrupting at msi9 vec 0
hdaudio1: HDA ver. 1.0, OSS 4, ISS 4, BSS 0, SDO 1, 64-bit
hdafg1 at hdaudio1: Realtek product 0897
hdafg1: DAC00 6ch: Speaker [Jack]
hdafg1: DAC01 2ch: HP Out [Jack]
hdafg1: ADC02 2ch: Line In [Jack], Mic In [Jack]
hdafg1: ADC03 2ch: Mic In [Jack]
hdafg1: DIG04 2ch: SPDIF Out [Jack]
hdafg1: 6ch/2ch 32000Hz 44100Hz 48000Hz 88200Hz 96000Hz 192000Hz PCM16 PCM20 PCM24 AC3
audio1 at hdafg1: playback, capture, full duplex, independent
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for recording
spkr2 at audio1: PC Speaker (synthesized)
wsbell at spkr2 not configured
ppb14 at pci0 dev 8 function 3: AMD 19h/6xh Internal PCIe GPP Bridge (rev. 0x00)
ppb14: PCI Express capability version 2 <Root Port of PCI-E Root Complex> x16 @ 16.0GT/s
pci15 at ppb14 bus 15
pci15: i/o space, memory space enabled, rd/line, wr/inv ok
xhci3 at pci15 dev 0 function 0: AMD 19h/6xh Secure USB BIOmetric (rev. 0x00)
xhci3: 64-bit DMA
xhci3: interrupting at msix10 vec 0
xhci3: xHCI version 1.20
usb6 at xhci3: USB revision 2.0
piixpm0 at pci0 dev 20 function 0: AMD X370/X399 SMBus Controller (rev. 0x71)
piixpm0: interrupting at SMI,
iic1 at piixpm0 port 0: I2C bus
iic2 at piixpm0 port 1: I2C bus
pcib0 at pci0 dev 20 function 3: AMD FCH LPC (rev. 0x51)
pchb5 at pci0 dev 24 function 0: AMD 19h/6xh Data Fabric 0 (rev. 0x00)
pchb6 at pci0 dev 24 function 1: AMD 19h/6xh Data Fabric 1 (rev. 0x00)
pchb7 at pci0 dev 24 function 2: AMD 19h/6xh Data Fabric 2 (rev. 0x00)
pchb8 at pci0 dev 24 function 3: AMD 19h/6xh Data Fabric 3 (rev. 0x00)
pchb9 at pci0 dev 24 function 4: AMD 19h/6xh Data Fabric 4 (rev. 0x00)
pchb10 at pci0 dev 24 function 5: AMD 19h/6xh Data Fabric 5 (rev. 0x00)
pchb11 at pci0 dev 24 function 6: AMD 19h/6xh Data Fabric 6 (rev. 0x00)
pchb12 at pci0 dev 24 function 7: AMD 19h/6xh Data Fabric 7 (rev. 0x00)
isa0 at pcib0
acpicpu0 at cpu0: ACPI CPU
acpicpu0: C1: FFH, lat 1 us, pow 0 mW
acpicpu0: C2: I/O, lat 18 us, pow 0 mW
acpicpu0: C3: I/O, lat 350 us, pow 0 mW
acpicpu0: P0: FFH, lat 1 us, pow 4625 mW, 3700 MHz
acpicpu0: P1: FFH, lat 1 us, pow 2550 mW, 3000 MHz
acpicpu1 at cpu1: ACPI CPU
acpicpu2 at cpu2: ACPI CPU
acpicpu3 at cpu3: ACPI CPU
acpicpu4 at cpu4: ACPI CPU
acpicpu5 at cpu5: ACPI CPU
acpicpu6 at cpu6: ACPI CPU
acpicpu7 at cpu7: ACPI CPU
acpicpu8 at cpu8: ACPI CPU
acpicpu9 at cpu9: ACPI CPU
acpicpu10 at cpu10: ACPI CPU
acpicpu11 at cpu11: ACPI CPU
acpicpu12 at cpu12: ACPI CPU
acpicpu13 at cpu13: ACPI CPU
acpicpu14 at cpu14: ACPI CPU
acpicpu15 at cpu15: ACPI CPU
acpicpu16 at cpu16: ACPI CPU
acpicpu17 at cpu17: ACPI CPU
acpicpu18 at cpu18: ACPI CPU
acpicpu19 at cpu19: ACPI CPU
acpicpu20 at cpu20: ACPI CPU
acpicpu21 at cpu21: ACPI CPU
acpicpu22 at cpu22: ACPI CPU
acpicpu23 at cpu23: ACPI CPU
timecounter: Timecounter “clockinterrupt” frequency 100 Hz quality 0
timecounter: Timecounter “TSC” frequency 3693065000 Hz quality 3000
uhub0 at usb0: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub0: 5 ports with 5 removable, self powered
uhub1 at usb1: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub1: 12 ports with 12 removable, self powered
uhub2 at usb2: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub2: 2 ports with 2 removable, self powered
uhub3 at usb3: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub3: 2 ports with 2 removable, self powered
uhub4 at usb4: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub4: 2 ports with 2 removable, self powered
uhub5 at usb5: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub5: 2 ports with 2 removable, self powered
uhub6 at usb6: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub6: 1 port with 1 removable, self powered
ld0: GPT GUID: 9b94f472-237d-4601-b411-c7262ae07e17
dk0 at ld0: “17abe03b-7c17-44cc-8dac-d3d56968b6b1”, 262144 blocks at 2048, type: msdos
dk1 at ld0: “c072c1e3-5d0b-4bd4-8789-7370295360e1”, 134897664 blocks at 264192, type: ffs
dk2 at ld0: “0291617a-ffbb-457e-b908-af9f61e5790f”, 67010560 blocks at 135161856, type: swap
dk3 at ld0: “ca370a40-b6d3-4b0a-9270-00acc6df4e2b”, 419430400 blocks at 202172416, type: ffs
dk4 at ld0: “8ae92095-2b67-450a-b3ac-32c912b78f08”, 1331922319 blocks at 621602816, type: ffs
IPsec: Initialized Security Association Processing.
ahcisata0 port 0: device present, speed: 1.5Gb/s
ahcisata0 port 1: device present, speed: 6.0Gb/s
uhub7 at uhub0 port 5: VIA Labs, Inc. (0x2109) USB3.0 Hub (0x0817), class 9/0, rev 3.10/90.23, addr 1
uhub7: 4 ports with 4 removable, self powered
uhub8 at uhub5 port 2: GenesysLogic (0x05e3) USB2.1 Hub (0x0610), class 9/0, rev 2.10/66.02, addr 1
uhub8: multiple transaction translators
umass0 at uhub4 port 1 configuration 1 interface 0
umass0: StoreJet Transcend (0x174c) StoreJet Transcend (0x5106), rev 3.00/80.00, addr 2
umass0: using SCSI over Bulk-Only
scsibus0 at umass0: 2 targets, 1 lun per target
sd0 at scsibus0 target 0 lun 0: <StoreJet, Transcend, 0> disk fixed
uhub8: 3 ports with 2 removable, self powered
sd0: 238 GB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 500118192 sectors
uhub9 at uhub1 port 5: VIA Labs, Inc. (0x2109) USB2.0 Hub (0x2817), class 9/0, rev 2.10/90.23, addr 2
uhub9: multiple transaction translators
uhub9: 4 ports with 4 removable, self powered
uhub10 at uhub4 port 2: GenesysLogic (0x05e3) USB3.1 Hub (0x0620), class 9/0, rev 3.20/66.02, addr 3
uhub10: 2 ports with 2 removable, self powered
uhidev0 at uhub8 port 3 configuration 1 interface 1
uhidev0: ENE (0x0cf2) AGON3 Light FX Device (0x7750), rev 2.00/1.00, addr 4, iclass 3/0
uhidev0: 236 report ids
uhid0 at uhidev0 reportid 236: input=64, output=64, feature=0
atapibus0 at atabus0: 1 targets
cd0 at atapibus0 drive 0: <HL-DT-ST DVDRAM GH22NS40, K5I98JK5513, NL01> cdrom removable
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
cd0(ahcisata0:0:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100) (using DMA)
wd0 at atabus1 drive 0
wd0: <ADATA SU650>
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 223 GB, 465141 cyl, 16 head, 63 sec, 512 bytes/sect x 468862128 sectors
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133), WRITE DMA FUA, NCQ (32 tags)
wd0(ahcisata0:1:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA), NCQ (31 tags)
uvideo0 at uhub9 port 1 configuration 1 interface 0: Generic (0x0bda) Streaming Webcam (0x5822), rev 2.10/22.08, addr 3
video0 at uvideo0: Generic (0x0bda) Streaming Webcam (0x5822), rev 2.10/22.08, addr 3
uaudio0 at uhub9 port 1 configuration 1 interface 2
uaudio0: Generic (0x0bda) Streaming Webcam (0x5822), rev 2.10/22.08, addr 3
uaudio0: audio rev 1.00
audio2 at uaudio0: capture
audio2: slinear_le:16 2ch 48000Hz, blk 12960 bytes (67.5ms) for recording
uhidev1 at uhub9 port 2 configuration 1 interface 0
uhidev1: SteelSeries (0x1038) SteelSeries Rival 110 Gaming Mouse (0x1729), rev 1.10/0.34, addr 4, iclass 3/0
uhid1 at uhidev1: input=32, output=32, feature=0
uhidev2 at uhub9 port 2 configuration 1 interface 1
uhidev2: SteelSeries (0x1038) SteelSeries Rival 110 Gaming Mouse (0x1729), rev 1.10/0.34, addr 4, iclass 3/1
ums0 at uhidev2: 6 buttons and Z dir
wsmouse0 at ums0 mux 0
uhub11 at uhub9 port 3: Genesys Logic (0x05e3) USB2.0 Hub (0x0608), class 9/0, rev 2.00/32.98, addr 5
uhub11: single transaction translator
uhub11: 4 ports with 4 removable, self powered
uhidev3 at uhub11 port 2 configuration 1 interface 0
uhidev3: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 6, iclass 3/1
ukbd0 at uhidev3
wskbd0 at ukbd0: console keyboard
uhidev4 at uhub11 port 2 configuration 1 interface 1
uhidev4: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 6, iclass 3/0
uhid2 at uhidev4: input=4, output=0, feature=0
uhidev5 at uhub11 port 2 configuration 1 interface 2
uhidev5: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 6, iclass 3/0
ukbd1 at uhidev5
wskbd1 at ukbd1 mux 1
uhidev6 at uhub1 port 7 configuration 1 interface 2
uhidev6: AsusTek Computer Inc. (0x0b05) AURA LED Controller (0x19af), rev 2.00/1.00, addr 7, iclass 3/0
uhidev6: 236 report ids
uhid3 at uhidev6 reportid 236: input=64, output=64, feature=0
ubt0 at uhub1 port 9
ubt0: Realtek (0x0b05) ASUS USB-BT500 (0x190e), rev 1.10/2.00, addr 8
swwdog0: software watchdog initialized
WARNING: 4 errors while detecting hardware; check system log.
boot device: ld0
root on dk1 dumps on dk2
root file system type: ffs
kern.module.path=/stand/amd64/10.1/modules
[drm] initializing kernel modesetting (NAVI10 0x1002:0x731F 0x1DA2:0xE411 0xC1).
[drm] register mmio base: 0xF6B00000
[drm] register mmio size: 524288
[drm] PCIE atomic ops is not supported
[drm] set register base offset for ATHUB
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for DF
[drm] set register base offset for DMU
[drm] set register base offset for GC
[drm] set register base offset for HDP
[drm] set register base offset for MMHUB
[drm] set register base offset for MP0
[drm] set register base offset for MP1
[drm] set register base offset for NBIF
[drm] set register base offset for NBIF
[drm] set register base offset for OSSSYS
[drm] set register base offset for SDMA0
[drm] set register base offset for SDMA1
[drm] set register base offset for SMUIO
[drm] set register base offset for THM
[drm] set register base offset for UVD
[drm] add ip block number 0 <nv_common>
[drm] add ip block number 1 <gmc_v10_0>
[drm] add ip block number 2 <navi10_ih>
[drm] add ip block number 3 <psp>
[drm] add ip block number 4 <smu>
[drm] add ip block number 5 <dm>
[drm] add ip block number 6 <gfx_v10_0>
[drm] add ip block number 7 <sdma_v5_0>
[drm] add ip block number 8 <vcn_v2_0>
[drm] add ip block number 9 <jpeg_v2_0>
ATOM BIOS: 113-1E4112U-O45
[drm] VCN decode is enabled in VM mode
[drm] VCN encode is enabled in VM mode
[drm] JPEG decode is enabled in VM mode
[drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit
amdgpu0: VRAM: 8176M 0x0000008000000000 – 0x00000081FEFFFFFF (8176M used)
amdgpu0: GART: 512M 0x0000000000000000 – 0x000000001FFFFFFF
[drm] Detected VRAM RAM=8176M, BAR=256M
[drm] RAM width 256bits GDDR6
Zone kernel: Available graphics memory: 9007199248577172 KiB
Zone dma32: Available graphics memory: 2097152 KiB
[drm] amdgpu: 8176M of VRAM memory ready
[drm] amdgpu: 8176M of GTT memory ready.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] PCIE GART of 512M enabled (table at 0x0000008000300000).
amdgpu0: interrupting at msi11 vec 0 (amdgpu0)
[drm] use_doorbell being set to: [true]
[drm] use_doorbell being set to: [true]
[drm] Found VCN firmware Version ENC: 1.14 DEC: 5 VEP: 0 Revision: 20
[drm] PSP loading VCN firmware
[drm] reserve 0x900000 from 0x81fe400000 for PSP TMR
amdgpu0: warn: RAS: ras ta ucode is not available
use vbios provided pptable
smu driver if version = 0x00000033, smu fw if version = 0x00000037, smu fw version = 0x002a4000 (42.64.0)
SMU driver if version not matched
SMU is initialized successfully!
[drm] Display Core initialized with v3.2.69!
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] Driver supports precise vblank timestamp query.
[drm] kiq ring mec 2 pipe 1 q 0
[drm] VCN decode and encode initialized successfully(under DPG Mode).
[drm] JPEG decode initialized successfully.
amdgpufb0 at amdgpu0
amdgpu0: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
amdgpu0: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
amdgpu0: ring comp_1.0.0 uses VM inv eng 4 on hub 0
amdgpu0: ring comp_1.1.0 uses VM inv eng 5 on hub 0
amdgpu0: ring comp_1.2.0 uses VM inv eng 6 on hub 0
amdgpu0: ring comp_1.3.0 uses VM inv eng 7 on hub 0
amdgpu0: ring comp_1.0.1 uses VM inv eng 8 on hub 0
amdgpu0: ring comp_1.1.1 uses VM inv eng 9 on hub 0
amdgpu0: ring comp_1.2.1 uses VM inv eng 10 on hub 0
amdgpu0: ring comp_1.3.1 uses VM inv eng 11 on hub 0
amdgpu0: ring kiq_2.1.0 uses VM inv eng 12 on hub 0
amdgpu0: ring sdma0 uses VM inv eng 13 on hub 0
amdgpu0: ring sdma1 uses VM inv eng 14 on hub 0
amdgpu0: ring vcn_dec uses VM inv eng 0 on hub 1
amdgpu0: ring vcn_enc0 uses VM inv eng 1 on hub 1
amdgpu0: ring vcn_enc1 uses VM inv eng 4 on hub 1
amdgpu0: ring jpeg_dec uses VM inv eng 5 on hub 1
[drm] Initialized amdgpu 3.36.0 20150101 for amdgpu0 on minor 0
amdgpufb0: framebuffer at 0xc04c9000, size 2560×1440, depth 32, stride 10240
wsdisplay0 at amdgpufb0 kbdmux 1: console (default, vt100 emulation), using wskbd0
wsmux1: connecting to wsdisplay0
wskbd1: connecting to wsdisplay0
aq0: link is UP: speed=10000
{drm:netbsd:gfx_v10_0_ring_test_ib+0x179} *ERROR* amdgpu: IB test timed out.
amdgpu0 {drm:netbsd:amdgpu_ib_ring_tests+0xdf} *ERROR* IB test failed on kiq_2.1.0 (-60).
{drm:netbsd:linux_workqueue_thread+0x15e} *ERROR* ib ring test failed (-60).
wsdisplay0: screen 1 added (default, vt100 emulation)
wsdisplay0: screen 2 added (default, vt100 emulation)
wsdisplay0: screen 3 added (default, vt100 emulation)
wsdisplay0: screen 4 added (default, vt100 emulation)
bthub0 at ubt0 local-bdaddr [_MAC_XXXXXXXXXX]

NetBSD

Resolving Memory Corruption in BIOS bootloader on VIA C7-Based Systems

2024-09-14 vezhlys

Following the resolution of the ALTINST mode issue, I returned to investigating the VIA C7 boot problem. Under certain circumstances, some Esther-based systems were experiencing a sudden reboot shortly after the kernel was loaded, which I was able to reproduce on my Biostar Viotech 3100+ motherboard. This led to a lengthy debugging process before I could finally identify the culprit!

Initial analysis

Typically, the bugs I encountered before were related to the NetBSD kernel or drivers. Initially, I assumed that this might also be an issue with the INSTALL kernel configuration because, during the early stages of investigation, the problem only occurred with the install image (not with the fully installed system on my SD card). A critical discovery in the debugging process was that the issue specifically occurred when ACPI 3.0 was enabled. I downloaded older releases to identify the first affected version and found that NetBSD 7.0 was the first to exhibit the symptoms.

To narrow down the problematic commit, I decided to install an older release on my USB image and build several kernels between different 6.99.x versions. However, I soon realized that the kernel wasn’t the issue – older 6.x kernels were also failing with the newer install images. At the same time, the install kernel was successfully booting from my SD card setup. At this point, it became clear that the problem was with the bootloader.

I then began building full distributions from various 6.99.x versions to pinpoint the commit responsible. This process was slow and painful, taking between 5 to 8 hours for each build. In hindsight, I could have just been building the bootloader code, but at the time, I didn’t know where the affected code was or how to build it. After several weeks of this repetitive process, I finally identified that the reboot issue began after the switch to GCC 4.8, specifically when the boot parameters were fixed in this particular commit. Unfortunately, this didn’t offer much insight into the underlying problem, and this approach reached a dead end.

At that point, I returned to the current code and started debugging the kernel’s behavior.

Kernel debugging

The boot log was printing only a few messages before the reboot, but it still provided a useful starting point, especially the last line: ‘pmap_kenter_pa: mapping already present’. I quickly located this message in the code and began investigating what was happening. The comment in the conditional block stated, ‘This should not happen,’ but clearly, it was. Eventually, the code called the kcpuset_copy() method, where both arguments were still undefined, leading to a null pointer dereference during the memcpy() call and triggering a sudden reboot.

Knowing this was helpful, but it didn’t explain why this ‘should not happen’ situation was occurring. Due to the early stage of the kernel boot process, getting a useful stack trace was either difficult or impossible. Nevertheless, I began tracing the pmap_kenter_pa() calls and hypothesizing where the call could have originated, especially since I knew that the global kcpuset_running parameter was not supposed to be set at this point. This is where comparing the behavior of ACPI 2.0 and ACPI 3.0 became useful. I inserted various debugging messages in the relevant parts of the code and compared the memory values between the two. This quickly led me to discover invalid virtual memory values that were dependent on the parameters passed from the bootloader (e.g., atdevbase, PDPpaddr).

It took some time to pinpoint exactly where the problematic code was being executed. My initial assumption was that the issue occurred somewhere in kern/init_main.c main(), but it turned out to be earlier, in init386() (specifically init386_pte0()), which was making the problematic pmap_kenter_pa() call. At this stage, kcpuset_running is not yet initialized, as that occurs later. However, since the conditional block causing the reboot wasn’t supposed to be executed so early in the process, no assertions were added to that part of the code.

Despite this progress, I was slowly hitting a dead end again. It was clear that something was wrong with the memory values, and code inspection showed their dependency on the bootloader’s input, potentially causing a reboot when these values deviated too far from the expected range. This also explained why the boot process sometimes succeeded. I could identify some workarounds at this point—such as ignoring the eblob value in the calculations—but these were not viable long-term solutions. It was becoming clear that I needed to start debugging the bootloader itself!

BIOS bootloader

At this point in the analysis, I already knew that the affected bootloader code was located in the sys/arch/i386/stand path and that it was part of the biosboot bootloader. With the help of other NetBSD developers and the documentation, I learned how to build the bootloader alone and install it into my installation image. This greatly sped up the debugging process, as I no longer needed to build the full distribution.

This process is relatively simple using the build.sh framework:

# build i386 cross-compile toolchain
./build.sh -T ../tools -O ../obj -U -j6 -mi386 tools
# to avoid searching for all dependencies repeatedly, build the distribution once using the build.sh framework
./build.sh -T ../tools -O ../obj -U -j6 -mi386 distribution
# navigate to the i386 bootloaders code folder
cd sys/arch/i386/stand/
# build the bootloaders and repeat the process as many times as necessary
../tools/bin/nbmake-i386 -j6 dependall
# install to destdir
../tools/bin/nbmake-i386 -j6 install

Then install the bios bootloader:

# mount NetBSD install image
mount /dev/sd0a /mnt
# copy secondary bootstrap to the root folder
sudo cp ../obj/destdir.i386/usr/mdec/boot /mnt/boot
# copy bootxx_* files (likely optional)
sudo cp ../obj/destdir.i386/usr/mdec/* /mnt/usr/mdec/
# install the primary bootstrap
installboot /dev/sd0a ../obj/destdir.i386/usr/mdec/bootxx_ffsv1
# unmount install image
umount /mnt

To avoid constantly mounting, unmounting, and re-attaching the USB stick, files can also be transferred via SSH and installed directly.

The main logic of the bootloader resides in the exec_netbsd() function, which is called by various i386 bootloaders with parameters from the primary bootloader’s input. This function loads the kernel, calculates its size, and performs related tasks. My debugging process focused on identifying where memory values were becoming incorrect. The marks[] array, where values are set during the kernel load process, was a major point of focus.

After multiple attempts, I discovered that the initial values in marks[] were correct immediately after the kernel was loaded, but they became corrupted by the end of the common_load_kernel() method. The corruption occurred despite only a few calls happening between these points, making it easier to identify the cause. The bi_getmemmap() call was pinpointed as the culprit. It was identified that the stack overflow occurred upon returning from this method, leading to stack corruption.

The issue was eventually narrowed down to the getmementry() call, which is invoked multiple times within bi_getmemmap(). Even a single call to getmementry() was enough to corrupt the stack right after returning from bi_getmemmap(). Debugging this was challenging because getmementry() is written in assembly code and has not been modified for many years.

With assistance, I eventually found that the allocated buffer for 5 words was actually writing to 6 words when ACPI 3.0 was enabled. It appeared that ACPI 3.0 extended the INT 0x15, EAX = 0xE820 BIOS function for memory detection from 20 bytes to 24 bytes to accommodate extended attributes. Only a few motherboards supported 24 bytes initially, while the specification required that the function return 20 bytes if requested, regardless of the actual support for 24 bytes. Some VIA systems shipped with a buggy BIOS that returned 24 bytes regardless.

The temporary buffer was not allocated for 24 bytes, causing a stack buffer overrun. The fix was to increase the buffer size from 5 to 6 words!

Conclusion

The Biostar Viotech 3100+ now boots successfully, with memory values consistent whether ACPI 3.0 is enabled or not. Changes have been applied to the NetBSD 10 and NetBSD 9 branches (as older releases are no longer supported). I must admit, this investigation was challenging: it involved a long process of narrowing down the issue, making incorrect and time-consuming decisions, countless reboots, and numerous bootloader builds and reinstalls. It required many long evenings to make slow progress or to rule out incorrect theories.

One might question whether spending time on outdated systems is worthwhile, and the answer might be no. However, like every solved mystery, it provides significant rewards in terms of knowledge and experience. I believe this exercise was valuable for me, and if even one user benefits from this fix, it will have been worth it. This motherboard has allowed me to address several issues: from a broken temperature sensor and a faulty ATLINST mode disable process to finally resolving the boot process failure. Now, I can give it some well-deserved rest and shift my focus to other tasks.

NetBSD

VIA temperature sensor and ALTINST mode issue

2024-07-24 vezhlys

VIA was always an underdog of the x86 CPU market, having only a fractional market share, mainly due to non-competitive performance and multiple other reasons. Despite that they had a unique niche and their small CPU design company – Centaur Technology, was closed just few years ago, however, their legacy still lives on with the Chinese Zhaoxin company, which evolves their design and uses Centaur CPU ID. I had been using VIA solutions since 2008, when I bought their unique VT310-DP motherboard. To my knowledge, it is the only known commercial Mini-ITX form-factor motherboard having two physical x86 CPUs (not cores). It was also used as a NetBSD NAS server for a while and sparked my first bug report on which I spent a lot of time debugging. It also led to a fix with the help of NetBSD developers and was caused by specific CPU functionality. This success eventually was a strong push for me to work more on NetBSD development in general. However, this story is not about this board or my NetBSD development history, but about another VIA specific issues I have recently encountered.

The story started from viac7temp(4) driver, which was being attached on VIA Nano CPUs but reporting 0s instead. The driver’s original implementation was using documented Fn_C0000002 CPUID instruction to retrieve CPU temperature from EDX register, thus the assumption was that it didn’t work with newer Nano models. I peeked at the Linux implementation and it was using MSRs (model-specific registers) instead, partially confirming my suspicion, since VIA Nano had a different MSR than C7 models. Unfortunately, those MSRs are not documented in any public datasheets available (Nano datasheets are not available at all). After some discussions I decided to rewrite our driver to use these MSRs as well, and the boost to finish my work came pretty quickly as one person hit the same issue on his VIA Nano based board. I have acquired an old Biostar Viotech 3100+ motherboard based on C7-D CPU to complement my Nano based systems and compare values between MSR and CPUID instruction. However, upon arrival temperature driver was also reporting 0s for C7-D CPU, even if MSR register worked. Unfortunately, my call for testing didn’t receive any responses, I was left guessing, if it was my specific CPU issue or some driver problem. Because of this, I was unable to compare CPUID instruction and MSR values but was able to make the decision easier to switch to MSR implementation. The final commit is shown in the link.

Typically the story would finish with that, but Biostar motherboard had some booting issues, which appeared to be related to BIOS ACPI settings and specific to the install image (or more likely to the bootloader used by it). I decided to spend some time investigating it and tested older NetBSD releases as a result, reaching 6.x release, where temperature driver reported correct value, proving that documented CPUID instruction should work! And here my hunch was telling me it may be related to the rosenbridge backdoor reported back in 2018. The backdoor was related to a so called Alternate Instruction Set (AIS) which could have been enabled and used in VIA C3 CPUs and were created for internal purposes (testing, debugging, etc). Their ability to bypass certain protection mechanisms were documented by VIA itself, and the backdoor took an advantage of them to gain unintended privileged access. It appeared that some models had it enabled by default from the factory, was it as a mistake or some other reasons. NetBSD development team introduced a quick fix to disable it explicitly to all VIA CPUs (among other bugs), which seemed to be an OK decision to do. Back in a day I tested few systems but found nothing unusual at first glance. That wasn’t the case though…

In order to test my theory, I commented out the line which was explicitly disabling the ATLINST mode and returned an older viac7temp temperature driver code, using CPUID instruction for testing and my theory appeared to be correct. CPUID instruction started to report value again! Fortunately, ALTSINST documentation is available in the internet these days which allowed me quickly to understand what may have been happening. ALTINST mode is available only in VIA C3 models, and only latest ones (Nehemiah) exposed an ability to check if they are enabled or supported at all. The NetBSD code was disabling it for all VIA models including C7, Nano and even current Zhaoxin models. Moreover, it was checking ACE (proprietary VIA advanced cryptography engine) flag to make a decision if instructions should be explicitly disabled. These are available in most VIA models after Nehemiah C5P, but not for earlier C3 models (Samuel, Samuel 2, Ezra, Nehemiah C5XL). The documentation was stating that alternate instruction set should not be attempted to enable on unsupported CPUs and could cause undocumented side effects, whose would depend on CPU model and revision! It appeared that temperature sensor for VIA C7 was exactly one of those side effects. Another one I noticed later with cpuctl identify <cpuindex> command, which was reporting less CPU features than expected. And this issue was affecting not only VIA C7, but later Nano models and even Nehemiah based Eden-N CPU, which was reporting that ALTINST mode is not supported by this CPU. Thus, I rewrote the code to disable alternate instruction set only if it is enabled and supported for C5P CPUs and for earlier I kept it explicit (those were not covered before). The final changes can be observed here. I don’t have early C3 systems and those can theoretically still have side effects on certain models, but at least they are pretty limited to the subset of the oldest models only. If you have any of these and see unusual behavior, bugs reports are welcome!

It was quite an unexpected turn of events for me but the moral of the story is that datasheets are important and sometimes broken functionality can escape the eyes for years. In the end, I was really happy to solve a seemingly small mystery of failing temperature sensor driver which led to the bug fix otherwise difficult to notice and ignored for many years.

NetBSD

NetBSD 9.4 and 8.3

2024-06-07 vezhlys

Around a month after the major NetBSD 10.0 release, two feature releases followed for the NetBSD 9 and 8 release branches. NetBSD 9.4 was formally released on 20th of April, 2024 and contains pretty big number of various improvements, bug and security fixes accumulated in almost two years. NetBSD 8.3 was released on 4th of May, 2024 and concluded the support for this release branch, no more bug or security fixes will be applied to it, pkgsrc also dropped support for it long ago, thus it is recommended to use later major releases (NetBSD 9 or 10). Nevertheless, it also contains quite a lot of changes since last 8.2 version was released around 4 years ago. It even contains a fix for the vte(4) driver bug which I was hunting for the several years. If there’s some reason you can’t use NetBSD 10.0, it is recommended to upgrade to the latest feature branches at least, preferably NetBSD 9.3.

NAS, NetBSD, pkgsrc

NetBSD NAS software setup

2024-06-07 vezhlys

Once boot process was solved, I needed to setup ZFS for my hard drives and several services like NFS and Samba, setup network bonding using the new dedicated lagg(4) interface with LACP protocol, which in turn would complete the major NAS functionality.

ZFS setup

Initial ZFS setup was pretty easy. Luckily, configuring ZFS modules (solaris, zfs) in modules.conf(5) file was enough to make it work, even if configuration file was located in chrooted root partition. I mainly followed the Creating ZFS pools on NetBSD article from the UnitedBSD , or more exactly the “Create a ZFS pool” section by creating a ZFS pool and datasets with the mount points. After that, adding “zfs=YES” line in rc.conf(5) file does the final trick in order to mount ZFS partitions in their intended locations. I also enabled de-duplication and gzip compression features. The main mistake followed after adding a second hard drive to the zpool, which was intended to be a mirrored drive, for which attach command should have been used. NetBSD’s zpool command doesn’t allow removal of the drive without proper redundancy and doesn’t support forced removal, thus I need to recreate the pool, which was a bit of painful setback. According to recommendations I scheduled once a month zpool scrub operation, but still need to setup scheduled snapshots in the nearest future.

Link aggregation

As mentioned previously QNAP TVS-675 system contains two expansion card slots using PCIe Gen3 x4 interface. Thanks to the cut at the back of the port, cards with x8 physical slot can also fit into the port (longer cards may not fit though without modifications, metal frame can block the insertion). The challenge in doing so that it was a very short distance between PSU and a slot bracket, which made it very difficult to unscrew it without removing the PSU first. Once the network card was physically in place, the major problem occurred while setting up the lagg(4) interface using link aggregation control protocol (LACP). It appeared that mcx(4) driver wasn’t setting up full-duplex data transmission required by the protocol. Fortunately, the fix was relatively easy and made it into NetBSD 10 release by enforcing full-duplex in the driver. Additionally, missing lagg parameters were documented in ifconfig(8) man page. After the fix, network bonding setup was pretty straightforward by creating /etc/ifconfig.lagg0 file:

create laggproto lacp laggport mcx0 laggport mcx1 up

I also created ifconfig.mcx0 and ifconfig.mcx1 with only up command and added net_interfaces=”mcx0,mcx1,lagg0″ line to /etc/rc.conf to control initialization order and ensure that mcx interfaces are up before lagg0 interface is created and initialized. For dhcpcd I added dhcpcd_flags=”-qM lagg0″ flags. After reboot my switch was happy to accept link aggregation with my NAS system.

Samba setup

Next step was to install and enable samba(8). The small issue was the missing xbase set required by the samba installation, since I was not aware of this requirement. I simply downloaded the required set and extracted it manually. Other than that I could mainly reuse configuration file from Linux system by only adjusting required paths and placing it in /usr/pkg/etc/samba/smb.conf location. Of course I needed to create a samba user (smbpasswd). Also worth to note that smbd, nmbd and winbindd services should be enabled instead of samba service, contrary to typical Linux experience.

NFS setup

NFS configuration was not compatible with the Linux one on the other hand and I needed to rewrite it from scratch. NetBSD “how to set up nfs and nis” and UnitedBSD NFS on NetBSD: server and client side wiki articles were a great guidance. To enable NFS properly I needed to add these line to /etc/rc.conf:

# NFS server
rpcbind=YES
nfs_server=YES
nfsd_flags=’-n8′
mountd=${nfs_server}
lockd=${nfs_server}
statd=${nfs_server}

And configure /etc/exports according to examples from the articles above. From client side I just needed to adjust /etc/fstab to the new NFS path.

Other notes

I also installed rtorrent as my torrent service and utilized cron to enable it after boot by adding this line to crontab configuration:

@reboot /usr/bin/tmux new-session -d '/usr/pkg/bin/rtorrent -D -I -n -o import=$ PWD/.rtorrent.rc'

.rtorrent.rc file just need to point to the session path, otherwise I kept it standard. After that tmux attach -d -t 0 command can be used to attach to the rtorrent session and CTRL+B D to detach from it.

In order to monitor HDD and its temperature I installed smartmontools utility. Current temperature can be retrieved using sudo smartctl -a /dev/rwd1|grep -i temp command (raw device should be used, thus rwd1 instead of wd1).

Finally I created the patch for the CPU temperature which didn’t make it to NetBSD 10 release, but hopefully will be available with NetBSD 10.1 through envstat(8) command. For time being I am using the patched kernel.

Overall my experience is quite positive with the new setup. There are still few improvements required, mainly for the data redundancy and potentially better power management and improved CPU support. The NAS device doesn’t like enclosed environments without proper airflow and my become extremely noisy in such case, however it works pretty silently be default. Actually the main noise was coming from 10-Gbit ethernet card, which has an active fan. Hard drives are also pretty audible unfortunately, thus SSDs would be preferred if silence is the priority.

NAS, NetBSD

Boot into SSD in QNAP TVS-675

2024-04-03 vezhlys

Historically, my first NAS system was running NetBSD operating system (5th release if I am not mistaken), however after a hardware update, I was forced to switch to the Debian Linux due to hardware support issues at that time. Since then I have used few different distributions for over a decade (mainly Arch and Artix). Several years ago I upgraded the underlying platform again with the hopes to use it for at least as long as my previous system. This NAS setup is based on Biostar FX9830M motherboard. My goal in doing so is to make setup as cheap as possible by scrapping various parts from my closet. Unfortunately, it didn’t workout as planned, mainly due to uncomfortably noisy operation of aforementioned motherboad’s CPU fan, which I have never managed to remedy (unusual fan connector and cooling solution is a limiting factor, requiring to do custom solutions without knowing if that solution will work). In addition, the compact case didn’t provide enough airflow leading to slightly overheating HDDs which may affect their operational lifetime. Thus, I decided that it may be a good chance to come back to a long time dream of switching back to NetBSD in my NAS setup and I acquired QNAP TVS-675 NAS system for this purpose.

Under the hood it uses Zhaoxin KaiXian KX-U6580 8-core x86-64 CPU, has 6 HDD bays, has an option to add two PCIe Gen 3 x4 cards (the slot allows to attach longer cards thanks to the cut at the back of it), and supports NVMe expansion slots. It is almost a typical x86-64 PC, just wrapped into a “fancy” case specifically designed for NAS purposes. It operates pretty silently by default, with only audible noise coming from HDDs themselves during heavy operations (once high capacity SSDs are cheap enough I may switch to them).

The installation of the NetBSD 10.0 didn’t bring any surprises and went smoothly, however I faced the first issue just after the first reboot. There was no support to boot directly from SATA SSD (limitation of the system’s BIOS). Only the USB boot devices are supported. As a result, I started to look into options somehow to start booting from USB, to switch the root system to the SSD partition at the subsequent stages of the boot process. After reading a few resources (will mention them at the end of the article) and consulting the NetBSD developers, I decided to use a pretty simple approach with SSD root partition being mounted to /altroot, where kernel eventually is being instructed to chroot to it. The approach is similar – to root on ZFS or CGD functionality, however I didn’t configure a separate ramdisk for that, at least now.

In order to achieve that, I needed to prepare a bootable USB flash drive. One can use a lengthy instructions with the UEFI in mind, or install a minimal system using installation media, however I took a lazy approach by dissecting provided installation media itself. I just mounted it on my main NetBSD system and deleted all unnecessary folders and files, updated netbsd kernel (I am building a custom one, but GENERIC can be used) and updated /etc/rc script by mounting required partitions, including SSD root to /altroot and finally setting init.root kernel option to /altroot, so that it would switch to it during boot process:

PATH=/sbin:/bin
export PATH

mount -u /
mount -t tmpfs tmpfs /tmp
mount /altroot
sysctl -w init.root=/altroot

# done, move on to multiuser mode
exit 0

To complete a setup, I added required fields to /etc/fstab by setting correct /altroot mount point to the SSD’s root partition.

NAME=<usbpartionid>		/		ffs	rw		1 1
tmpfs			/tmp		tmpfs	rw		0 0
NAME=<ssdpartitionid>			/altroot	ffs	ro,log	1 1

The important part was to mount /altroot as read-only (ro), otherwise automatic filesystem check kicked-in and disrupted the boot process (it can’t check rw mounted partitions), requiring for the manual interaction. It is not an issue, since root partition will remount in rw mode by reading SSDs /etc/fstab. If there’s a need to change some files in /altroot before chroot (like rndseed for example), automount can be still rw but rc script should remount /altroot manually as read only shortly before sysctl command. Alternative approach may be to skip remounting root partition at all, but I haven’t tried it.

After reboot the system successfully booted and switched to SSD root folder!

Ideally I would like to avoid having USB flash drive being attached at all. I believe that integrated USB DISK module can be utilized somehow, but I haven’t explored that just yet, since i I don’t want to mess up the default boot configuration for the their own custom OS and it needs more time and skills to implement. For the time being, I would likely buy a very short USB flash driver, similar to Intenso Slim Line to make protrusion from the case as minimal as it can be.

The next step will be to setup my hard drives to using ZFS file system, setup NFS and samba as well as network with lagg(4) link aggregation. I am unsure at the moment, where I should load zfs modules, should it be before the chroot operation happens or it can be loaded after. Currently I am utilizing SSD root partition’s /etc/modules.conf file, which loads modules correctly, however I am not certain if it won’t be too late for mounting ZFS partitions automatically. I will definitely explore that in the next post.

Few useful resources on this topic:
HowTo: Making a bootable ISO w/ miniroot.kmod etc.
Building a NetBSD ramdisk kernel
Root On ZFS
NetBSD Full-Disk Encryption with CGD
Building NetBSD system components

NetBSD

NetBSD 10.0 released!

2024-03-31 vezhlys

After years of development NetBSD 10 reached the finish line and the final 10.0 release was officially announced yesterday. It brings multiple improvements, updates and new features in the all areas of the system, being it performance improvements, hardware support, security, virtualization, networking stack, storage or applications and APIs. Please check release announcement and CHANGES for the more details. The release announcement doesn’t mention experimental igc(4) driver for Intel I225/I226 2.5G Ethernet adapters. I have those on one of my systems and can confirm that they work in at least simple setup. The important update was a DRM sync with Linux 5.6. Unfortunately, it didn’t go smoothly, multiple issues remain with graphics support with plans to improve it in the future releases. From my personal experience I can currently use Radeon RX5700XT with some caveats, which wasn’t even supported in previous releases.

Personally for me this release is quite important in few ways, it is the first major release since I officially became a developer myself and it brings important updates to hardware I use or plan to utilize in near future like lagg(4) link aggregation interface with mcx(4) 10Gbit controller or above mentioned RX5700XT and igc(4) support. I can’t say my own contributions were important (few bug and build fixes, and tons of spelling fixes in documentation, log messages and comments), however I believe I invested considerably more time into this release than any other previous one in some less direct ways like reporting, testing and facilitating bug fixes. Few last minute fixes were directly related to my bug reports.

The release can be downloaded from CDN service or any other project mirrors. Please don’t hesitate to try it and report bugs! As usual, it is strongly recommended to update for users of earlier NetBSD releases.

Full dmesg below:

NetBSD 10.0 on Ryzen 5600/Gigabyte A520 Aorus Elite/Radeon RX5700XT

NetBSD 10.0 (GENERIC_AMDGPU) #8: Sun Mar 31 22:50:50 EEST 2024
andriusv@agraphic-pc:/home/andriusv/obj/sys/arch/amd64/compile/GENERIC_AMDGPU
total memory = 32691 MB
avail memory = 31592 MB
timecounter: Timecounters tick every 10.000 msec
Kernelized RAIDframe activated
RTC BIOS diagnostic error 0xf
timecounter: Timecounter “i8254” frequency 1193182 Hz quality 100
efi: systbl at pa bdb74018
mainbus0 (root)
ACPI: RSDP 0x00000000BCEBD014 000024 (v02 ALASKA)
ACPI: XSDT 0x00000000BCEBC728 0000EC (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: FACP 0x00000000BC7D8000 000114 (v06 ALASKA A M I 01072009 AMI 00010013)
ACPI: DSDT 0x00000000BC6CF000 0069DC (v02 ALASKA A M I 01072009 INTL 20190509)
ACPI: FACS 0x00000000BCEB7000 000040
ACPI: SSDT 0x00000000BC7E7000 00AFB8 (v02 GBT GSWApp 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC7DE000 008CE9 (v02 AMD AmdTable 00000002 MSFT 04000000)
ACPI: SSDT 0x00000000BC7DA000 003D7C (v02 AMD AMD AOD 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC7D9000 0001AD (v02 ALASKA CPUSSDT 01072009 AMI 01072009)
ACPI: FIDT 0x00000000BC7D1000 00009C (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: MCFG 0x00000000BC7D0000 00003C (v01 ALASKA A M I 01072009 MSFT 00010013)
ACPI: HPET 0x00000000BC7CF000 000038 (v01 ALASKA A M I 01072009 AMI 00000005)
ACPI: IVRS 0x00000000BC7CE000 0000D0 (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: FPDT 0x00000000BC7CD000 000044 (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: BGRT 0x00000000BC7CC000 000038 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: TPM2 0x00000000BC7CB000 00004C (v04 ALASKA A M I 00000001 AMI 00000000)
ACPI: PCCT 0x00000000BC7CA000 00006E (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: SSDT 0x00000000BC7C6000 0030FB (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: CRAT 0x00000000BC7C5000 000B90 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: CDIT 0x00000000BC7C4000 000029 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: WPBT 0x00000000BC6E0000 000038 (v01 ALASKA A M I 00000001 GBT 20181220)
ACPI: SSDT 0x00000000BC6DF000 00068E (v02 AMD ArticDGP 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC6DD000 001522 (v02 AMD ArticTPX 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC6DC000 000788 (v02 AMD ArticNOI 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC6D8000 003A23 (v02 AMD ArticN 00000001 INTL 20190509)
ACPI: WSMT 0x00000000BC6D7000 000028 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: APIC 0x00000000BC6D6000 00015E (v04 ALASKA A M I 01072009 AMI 00010013)
ACPI: SSDT 0x00000000BC7D6000 00147F (v02 AMD ArticC 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC7D5000 0000BF (v01 AMD AmdTable 00001000 INTL 20190509)
ACPI: 12 ACPI AML tables successfully acquired and loaded
ioapic0 at mainbus0 apid 13: pa 0xfec00000, version 0x21, 24 pins
ioapic1 at mainbus0 apid 14: pa 0xfec01000, version 0x21, 32 pins
cpu0 at mainbus0 apid 0
cpu0: Use mfence to serialize rdtsc
cpu0: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu0: node 0, package 0, core 0, smt 0
cpu0: SVM disabled by the BIOS
cpu1 at mainbus0 apid 2
cpu1: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu1: node 0, package 0, core 1, smt 0
cpu2 at mainbus0 apid 4
cpu2: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu2: node 0, package 0, core 2, smt 0
cpu3 at mainbus0 apid 6
cpu3: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu3: node 0, package 0, core 3, smt 0
cpu4 at mainbus0 apid 8
cpu4: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu4: node 0, package 0, core 4, smt 0
cpu5 at mainbus0 apid 10
cpu5: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu5: node 0, package 0, core 5, smt 0
cpu6 at mainbus0 apid 1
cpu6: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu6: node 0, package 0, core 0, smt 1
cpu7 at mainbus0 apid 3
cpu7: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu7: node 0, package 0, core 1, smt 1
cpu8 at mainbus0 apid 5
cpu8: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu8: node 0, package 0, core 2, smt 1
cpu9 at mainbus0 apid 7
cpu9: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu9: node 0, package 0, core 3, smt 1
cpu10 at mainbus0 apid 9
cpu10: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu10: node 0, package 0, core 4, smt 1
cpu11 at mainbus0 apid 11
cpu11: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu11: node 0, package 0, core 5, smt 1
acpi0 at mainbus0: Intel ACPICA 20221020
acpi0: X/RSDT: OemId , AslId
acpi0: autoconfiguration error: invalid PCI address for D003
acpi0: autoconfiguration error: invalid PCI address for D00A
acpi0: MCFG: segment 0, bus 0-127, address 0x00000000f0000000
acpi0: SCI interrupting at int 9
acpi0: fixed power button present
timecounter: Timecounter “ACPI-Safe” frequency 3579545 Hz quality 900
hpet0 at acpi0: high precision event timer (mem 0xfed00000-0xfed00400)
timecounter: Timecounter “hpet0” frequency 14318180 Hz quality 2000
AMDN (PNP0C01) at acpi0 not configured
attimer1 at acpi0 (TMR, PNP0100): io 0x40-0x43 irq 0
pcppi1 at acpi0 (SPKR, PNP0800): io 0x61
spkr0 at pcppi1: PC Speaker
wsbell at spkr0 not configured
midi0 at pcppi1: PC speaker
sysbeep0 at pcppi1
com0 at acpi0 (UAR1, PNP0501-0): io 0x3f8-0x3ff irq 4
com0: ns16550a, 16-byte FIFO
acpibut0 at acpi0 (PWRB, PNP0C0C-170): ACPI Power Button
GPIO (AMDI0030) at acpi0 not configured
TPM (MSFT0101) at acpi0 not configured
PTIO (AMDIF030) at acpi0 not configured
acpitz0 at acpi0 (TZ10)
acpitz0: levels: critical 20.8 C, hot 19.8 C, passive 16.8 C, passive cooling
acpitz1 at acpi0 (UAD0)
acpitz1: levels: critical 20.8 C, hot 19.8 C, passive 16.8 C, passive cooling
acpiwmi0 at acpi0 (GSA1, PNP0C14-GSADEV0): ACPI WMI Interface
acpiwmibus at acpiwmi0 not configured
acpiwmi1 at acpi0 (AOD, PNP0C14-AOD): ACPI WMI Interface
acpiwmibus at acpiwmi1 not configured
ACPI: Enabled 1 GPEs in block 00 to 1F
attimer1: attached to pcppi1
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
amdsmn0 at pci0 dev 0 function 0: AMD System Management Network
amdzentemp0 at amdsmn0: AMD CPU Temperature Sensors (Family19h)
AMD Family17h/7xh IOMMU (IOMMU system) at pci0 dev 0 function 2 not configured
pchb0 at pci0 dev 1 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb0 at pci0 dev 1 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb0: PCI Express capability version 2 x4 @ 8.0GT/s
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
nvme0 at pci1 dev 0 function 0: Western Digital (SanDisk) product 5019 (rev. 0x01)
nvme0: NVMe 1.4
nvme0: for admin queue interrupting at msix0 vec 0
nvme0: WDC WDS100T2B0C-00PXH0, firmware 233010WD, serial 21281W452002
nvme0: for io queue 1 interrupting at msix0 vec 1 affinity to cpu0
nvme0: for io queue 2 interrupting at msix0 vec 2 affinity to cpu1
nvme0: for io queue 3 interrupting at msix0 vec 3 affinity to cpu2
nvme0: for io queue 4 interrupting at msix0 vec 4 affinity to cpu3
nvme0: for io queue 5 interrupting at msix0 vec 5 affinity to cpu4
nvme0: for io queue 6 interrupting at msix0 vec 6 affinity to cpu5
nvme0: for io queue 7 interrupting at msix0 vec 7 affinity to cpu6
nvme0: for io queue 8 interrupting at msix0 vec 8 affinity to cpu7
nvme0: for io queue 9 interrupting at msix0 vec 9 affinity to cpu8
nvme0: for io queue 10 interrupting at msix0 vec 10 affinity to cpu9
nvme0: for io queue 11 interrupting at msix0 vec 11 affinity to cpu10
nvme0: for io queue 12 interrupting at msix0 vec 12 affinity to cpu11
ld0 at nvme0 nsid 1
ld0: 931 GB, 121601 cyl, 255 head, 63 sec, 512 bytes/sect x 1953525168 sectors
ppb1 at pci0 dev 1 function 2: AMD 17h/7xh PCIe (rev. 0x00)
ppb1: PCI Express capability version 2 x8 @ 8.0GT/s
ppb1: link is x4 @ 8.0GT/s
pci2 at ppb1 bus 2
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
xhci0 at pci2 dev 0 function 0: AMD product 43ec (rev. 0x00)
xhci0: 64-bit DMA
xhci0: interrupting at msix1 vec 0
xhci0: xHCI version 1.10
usb0 at xhci0: USB revision 3.1
usb1 at xhci0: USB revision 2.0
ahcisata0 at pci2 dev 0 function 1: AMD 500 Series AHCI (rev. 0x00)
ahcisata0: 64-bit DMA
ahcisata0: AHCI revision 1.31, 6 ports, 32 slots, CAP 0xef36ff25
ahcisata0: interrupting at msi2 vec 0
atabus0 at ahcisata0 channel 0
atabus1 at ahcisata0 channel 1
atabus2 at ahcisata0 channel 4
atabus3 at ahcisata0 channel 5
ppb2 at pci2 dev 0 function 2: AMD 500 Series PCIe (rev. 0x00)
ppb2: PCI Express capability version 2
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled, rd/line, wr/inv ok
ppb3 at pci3 dev 0 function 0: AMD 500 Series PCIe (rev. 0x00)
ppb3: PCI Express capability version 2 x2 @ 8.0GT/s
pci4 at ppb3 bus 4
pci4: i/o space, memory space enabled, rd/line, wr/inv ok
aq0 at pci4 dev 0 function 0: Aquantia AQC100 10 Gigabit Network Adapter (rev. 0x02)
aq0: Atlantic revision B1, F/W version 3.1.58
aq0: fw2x> F/W capabilities=0x63c0001900007f20
aq0: Etheraddr: [_MAC_XXXXXXXXXX]
pchb1 at pci0 dev 2 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb2 at pci0 dev 3 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb4 at pci0 dev 3 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb4: PCI Express capability version 2 x16 @ 8.0GT/s
pci5 at ppb4 bus 5
pci5: i/o space, memory space enabled, rd/line, wr/inv ok
ppb5 at pci5 dev 0 function 0: ATI Technologies product 1478 (rev. 0xc1)
ppb5: PCI Express capability version 2
pci6 at ppb5 bus 6
pci6: i/o space, memory space enabled, rd/line, wr/inv ok
ppb6 at pci6 dev 0 function 0: ATI Technologies product 1479 (rev. 0x00)
ppb6: PCI Express capability version 2 x16 @ 16.0GT/s
pci7 at ppb6 bus 7
pci7: i/o space, memory space enabled, rd/line, wr/inv ok
amdgpu0 at pci7 dev 0 function 0: ATI Technologies Radeon RX 5600 OEM/5600 XT / 5700/5700 XT (rev. 0xc1)
hdaudio0 at pci7 dev 0 function 1: HD Audio Controller
hdaudio0: interrupting at msi4 vec 0
hdaudio0: HDA ver. 1.0, OSS 6, ISS 0, BSS 0, SDO 1, 64-bit
hdafg0 at hdaudio0: ATI R6xx HDMI
hdafg0: HDMI00 2ch: Digital Out [Jack]
hdafg0: HDMI01 2ch: Digital Out [Jack]
hdafg0: HDMI02 2ch: Digital Out [Jack]
hdafg0: HDMI03 2ch: Digital Out [Jack]
hdafg0: HDMI04 2ch: Digital Out [Jack]
hdafg0: HDMI05 2ch: Digital Out [Jack]
hdafg0: 2ch/0ch 32000Hz 44100Hz 48000Hz PCM16 AC3
audio0 at hdafg0: playback
audio0: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
spkr1 at audio0: PC Speaker (synthesized)
wsbell at spkr1 not configured
pchb3 at pci0 dev 4 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb4 at pci0 dev 5 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb5 at pci0 dev 7 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb7 at pci0 dev 7 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb7: PCI Express capability version 2 x16 @ 16.0GT/s
pci8 at ppb7 bus 8
pci8: i/o space, memory space enabled, rd/line, wr/inv ok
AMD product 148a (non-essential instrumentation, subclass 0x00) at pci8 dev 0 function 0 not configured
pchb6 at pci0 dev 8 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb8 at pci0 dev 8 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb8: PCI Express capability version 2 x16 @ 16.0GT/s
pci9 at ppb8 bus 9
pci9: i/o space, memory space enabled, rd/line, wr/inv ok
AMD Family17h/7xh Reserved SPP (non-essential instrumentation, subclass 0x00) at pci9 dev 0 function 0 not configured
amdccp0 at pci9 dev 0 function 1: AMD Cryptographic Coprocessor
xhci1 at pci9 dev 0 function 3: AMD Family17h/7xh USB 3.0 Host Controller (rev. 0x00)
xhci1: 64-bit DMA
xhci1: interrupting at msix5 vec 0
xhci1: xHCI version 1.10
usb2 at xhci1: USB revision 3.1
usb3 at xhci1: USB revision 2.0
hdaudio1 at pci9 dev 0 function 4: HD Audio Controller
hdaudio1: interrupting at msi6 vec 0
hdaudio1: HDA ver. 1.0, OSS 4, ISS 4, BSS 0, SDO 1, 64-bit
hdafg1 at hdaudio1: Realtek product 0b00
hdafg1: DAC00 6ch: Speaker [Jack]
hdafg1: DAC01 2ch: HP Out [Jack]
hdafg1: DIG02 2ch: SPDIF Out [Jack]
hdafg1: ADC03 2ch: Line In [Jack], Mic In [Jack]
hdafg1: ADC04 2ch: Mic In [Jack]
hdafg1: 6ch/2ch 32000Hz 44100Hz 48000Hz 88200Hz 96000Hz 192000Hz PCM16 PCM20 PCM24 AC3
audio1 at hdafg1: playback, capture, full duplex, independent
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for recording
spkr2 at audio1: PC Speaker (synthesized)
wsbell at spkr2 not configured
piixpm0 at pci0 dev 20 function 0: AMD X370/X399 SMBus Controller (rev. 0x61)
piixpm0: interrupting at SMI,
iic0 at piixpm0 port 0: I2C bus
iic1 at piixpm0 port 1: I2C bus
pcib0 at pci0 dev 20 function 3: AMD FCH LPC (rev. 0x51)
pchb7 at pci0 dev 24 function 0: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb8 at pci0 dev 24 function 1: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb9 at pci0 dev 24 function 2: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb10 at pci0 dev 24 function 3: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb11 at pci0 dev 24 function 4: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb12 at pci0 dev 24 function 5: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb13 at pci0 dev 24 function 6: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb14 at pci0 dev 24 function 7: AMD 17h/7xh Data Fabric (rev. 0x00)
isa0 at pcib0
pckbc0 at isa0 port 0x60-0x64
acpicpu0 at cpu0: ACPI CPU
acpicpu0: C1: FFH, lat 1 us, pow 0 mW
acpicpu0: C2: I/O, lat 18 us, pow 0 mW
acpicpu0: P0: FFH, lat 1 us, pow 3850 mW, 3500 MHz
acpicpu0: P1: FFH, lat 1 us, pow 2800 mW, 2800 MHz
acpicpu0: P2: FFH, lat 1 us, pow 1980 mW, 2200 MHz
acpicpu1 at cpu1: ACPI CPU
acpicpu2 at cpu2: ACPI CPU
acpicpu3 at cpu3: ACPI CPU
acpicpu4 at cpu4: ACPI CPU
acpicpu5 at cpu5: ACPI CPU
acpicpu6 at cpu6: ACPI CPU
acpicpu7 at cpu7: ACPI CPU
acpicpu8 at cpu8: ACPI CPU
acpicpu9 at cpu9: ACPI CPU
acpicpu10 at cpu10: ACPI CPU
acpicpu11 at cpu11: ACPI CPU
timecounter: Timecounter “clockinterrupt” frequency 100 Hz quality 0
timecounter: Timecounter “TSC” frequency 3493442000 Hz quality 3000
uhub0 at usb0: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub0: 3 ports with 3 removable, self powered
uhub1 at usb1: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub1: 9 ports with 9 removable, self powered
uhub2 at usb2: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub2: 4 ports with 4 removable, self powered
uhub3 at usb3: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub3: 4 ports with 4 removable, self powered
ld0: GPT GUID: 9b94f472-237d-4601-b411-c7262ae07e17
dk0 at ld0: “17abe03b-7c17-44cc-8dac-d3d56968b6b1”, 262144 blocks at 2048, type: msdos
dk1 at ld0: “c072c1e3-5d0b-4bd4-8789-7370295360e1”, 134897664 blocks at 264192, type: ffs
dk2 at ld0: “0291617a-ffbb-457e-b908-af9f61e5790f”, 67010560 blocks at 135161856, type: swap
dk3 at ld0: “ca370a40-b6d3-4b0a-9270-00acc6df4e2b”, 419430400 blocks at 202172416, type: ffs
dk4 at ld0: “8ae92095-2b67-450a-b3ac-32c912b78f08”, 1331922319 blocks at 621602816, type: ffs
IPsec: Initialized Security Association Processing.
ahcisata0 port 0: device present, speed: 6.0Gb/s
ahcisata0 port 1: device present, speed: 1.5Gb/s
uhub4 at uhub1 port 3: Genesys Logic (0x05e3) USB2.0 Hub (0x0608), class 9/0, rev 2.00/60.90, addr 1
uhub4: single transaction translator
uhub4: 4 ports with 4 removable, self powered
uhub5 at uhub3 port 2: GenesysLogic (0x05e3) USB2.1 Hub (0x0610), class 9/0, rev 2.10/66.02, addr 1
uhub5: multiple transaction translators
uhub5: 3 ports with 2 removable, self powered
umass0 at uhub2 port 1 configuration 1 interface 0
umass0: Generic (0x21c4) USB Storage (0xb064), rev 3.20/0.09, addr 2
umass0: using SCSI over Bulk-Only
scsibus0 at umass0: 2 targets, 3 luns per target
sd0 at scsibus0 target 0 lun 0: disk removable
sd0: drive offline
autoconfiguration error: sd0: unable to open device, error = 19
sd1 at scsibus0 target 0 lun 1: disk removable
sd1: drive offline
autoconfiguration error: sd1: unable to open device, error = 19
sd2 at scsibus0 target 0 lun 2: disk removable
sd2: drive offline
autoconfiguration error: sd2: unable to open device, error = 19
uhub6 at uhub2 port 2: GenesysLogic (0x05e3) USB3.1 Hub (0x0620), class 9/0, rev 3.20/66.02, addr 3
uhub6: 2 ports with 2 removable, self powered
uhidev0 at uhub5 port 3 configuration 1 interface 1
uhidev0: ENE (0x0cf2) AGON3 Light FX Device (0x7750), rev 2.00/1.00, addr 4, iclass 3/0
uhidev0: 236 report ids
uhid0 at uhidev0 reportid 236: input=64, output=64, feature=0
ubt0 at uhub4 port 4
ubt0: Cambridge Silicon Radio (0x0a12) BT DONGLE10 (0x0001), rev 2.00/88.91, addr 2
wd0 at atabus0 drive 0
wd0:
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 223 GB, 465141 cyl, 16 head, 63 sec, 512 bytes/sect x 468862128 sectors
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133), WRITE DMA FUA, NCQ (32 tags)
wd0(ahcisata0:0:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA), NCQ (31 tags)
atapibus0 at atabus1: 1 targets
cd0 at atapibus0 drive 0: cdrom removable
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
cd0(ahcisata0:1:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100) (using DMA)
uhub7 at uhub3 port 3: VIA Labs, Inc. (0x2109) USB2.0 Hub (0x2817), class 9/0, rev 2.10/90.23, addr 5
uhub7: multiple transaction translators
uhub7: 4 ports with 4 removable, self powered
uhub8 at uhub2 port 3: VIA Labs, Inc. (0x2109) USB3.0 Hub (0x0817), class 9/0, rev 3.10/90.23, addr 6
uhub8: 4 ports with 4 removable, self powered
uhidev1 at uhub1 port 4 configuration 1 interface 0
uhidev1: ITE Tech. Inc. (0x048d) ITE Device (0x5702), rev 2.00/0.01, addr 3, iclass 3/0
uhidev1: 204 report ids
uhid1 at uhidev1 reportid 90: input=0, output=0, feature=16
uhid2 at uhidev1 reportid 204: input=0, output=0, feature=63
umass1 at uhub2 port 4 configuration 1 interface 0
umass1: StoreJet Transcend (0x174c) StoreJet Transcend (0x5106), rev 3.00/80.00, addr 7
umass1: using SCSI over Bulk-Only
scsibus1 at umass1: 2 targets, 1 lun per target
sd3 at scsibus1 target 0 lun 0: disk fixed
sd3: 238 GB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 500118192 sectors
uhub9 at uhub7 port 2: Genesys Logic (0x05e3) USB2.0 Hub (0x0608), class 9/0, rev 2.00/32.98, addr 8
uhub9: single transaction translator
uhub9: 4 ports with 4 removable, self powered
uhidev2 at uhub9 port 2 configuration 1 interface 0
uhidev2: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 9, iclass 3/1
ukbd0 at uhidev2
wskbd0 at ukbd0: console keyboard
uhidev3 at uhub9 port 2 configuration 1 interface 1
uhidev3: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 9, iclass 3/0
uhid3 at uhidev3: input=4, output=0, feature=0
uhidev4 at uhub9 port 2 configuration 1 interface 2
uhidev4: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 9, iclass 3/0
ukbd1 at uhidev4
wskbd1 at ukbd1 mux 1
uhidev5 at uhub7 port 3 configuration 1 interface 0
uhidev5: Kensington (0x047d) Orbit Fusion Wireless Trackball (0x807b), rev 1.10/10.01, addr 10, iclass 3/1
ums0 at uhidev5: 8 buttons, W and Z dirs
wsmouse0 at ums0 mux 0
uhidev6 at uhub7 port 3 configuration 1 interface 1
uhidev6: Kensington (0x047d) Orbit Fusion Wireless Trackball (0x807b), rev 1.10/10.01, addr 10, iclass 3/0
uhidev6: 1 report ids
uhid4 at uhidev6 reportid 1: input=2, output=0, feature=0
uhidev7 at uhub7 port 3 configuration 1 interface 2
uhidev7: Kensington (0x047d) Orbit Fusion Wireless Trackball (0x807b), rev 1.10/10.01, addr 10, iclass 3/0
uhid5 at uhidev7: input=16, output=16, feature=0
uaudio0 at uhub7 port 4 configuration 1 interface 0
uaudio0: C-Media Electronics Inc. (0x0d8c) Genesis Radium 100 (0x0014), rev 1.10/1.00, addr 11
uaudio0: audio rev 1.00
audio2 at uaudio0: playback, capture, full duplex, independent
audio2: slinear_le:16 2ch 48000Hz, blk 11520 bytes (60ms) for playback
audio2: slinear_le:16 1ch 48000Hz, blk 6000 bytes (62.5ms) for recording
spkr3 at audio2: PC Speaker (synthesized)
wsbell at spkr3 not configured
uhidev8 at uhub7 port 4 configuration 1 interface 3
uhidev8: C-Media Electronics Inc. (0x0d8c) Genesis Radium 100 (0x0014), rev 1.10/1.00, addr 11, iclass 3/0
uhid6 at uhidev8: input=4, output=4, feature=0
swwdog0: software watchdog initialized
WARNING: 5 errors while detecting hardware; check system log.
boot device: ld0
root on dk1 dumps on dk2
root file system type: ffs
kern.module.path=/stand/amd64/10.0/modules
[drm] initializing kernel modesetting (NAVI10 0x1002:0x731F 0x1DA2:0xE411 0xC1).
[drm] register mmio base: 0xFCA00000
[drm] register mmio size: 524288
[drm] set register base offset for ATHUB
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for DF
[drm] set register base offset for DMU
[drm] set register base offset for GC
[drm] set register base offset for HDP
[drm] set register base offset for MMHUB
[drm] set register base offset for MP0
[drm] set register base offset for MP1
[drm] set register base offset for NBIF
[drm] set register base offset for NBIF
[drm] set register base offset for OSSSYS
[drm] set register base offset for SDMA0
[drm] set register base offset for SDMA1
[drm] set register base offset for SMUIO
[drm] set register base offset for THM
[drm] set register base offset for UVD
[drm] add ip block number 0
[drm] add ip block number 1
[drm] add ip block number 2
[drm] add ip block number 3
[drm] add ip block number 4
[drm] add ip block number 5
[drm] add ip block number 6
[drm] add ip block number 7
[drm] add ip block number 8
[drm] add ip block number 9
ATOM BIOS: 113-1E4112U-O45
[drm] VCN decode is enabled in VM mode
[drm] VCN encode is enabled in VM mode
[drm] JPEG decode is enabled in VM mode
[drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit
amdgpu0: VRAM: 8176M 0x0000008000000000 – 0x00000081FEFFFFFF (8176M used)
amdgpu0: GART: 512M 0x0000000000000000 – 0x000000001FFFFFFF
[drm] Detected VRAM RAM=8176M, BAR=256M
[drm] RAM width 256bits GDDR6
Zone kernel: Available graphics memory: 9007199253296414 KiB
Zone dma32: Available graphics memory: 2097152 KiB
[drm] amdgpu: 8176M of VRAM memory ready
[drm] amdgpu: 8176M of GTT memory ready.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] PCIE GART of 512M enabled (table at 0x0000008000300000).
amdgpu0: interrupting at msi7 vec 0 (amdgpu0)
[drm] use_doorbell being set to: [true]
[drm] use_doorbell being set to: [true]
[drm] Found VCN firmware Version ENC: 1.14 DEC: 5 VEP: 0 Revision: 20
[drm] PSP loading VCN firmware
[drm] reserve 0x900000 from 0x81fe400000 for PSP TMR
amdgpu0: warn: RAS: ras ta ucode is not available
use vbios provided pptable
smu driver if version = 0x00000033, smu fw if version = 0x00000037, smu fw version = 0x002a4000 (42.64.0)
SMU driver if version not matched
OD: Gfxclk: (800, 2054)
OD: Gfx1: (800, 2858)
OD: Gfx2: (1427, 3267)
OD: Gfx3: (2054, 4780)
OD: UclkFmax: 875
OD: OverDrivePct: 0
SMU is initialized successfully!
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 1482031344
[drm] Display Core initialized with v3.2.69!
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 1
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 0
[BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 54000
100 rate = 14
101 lane = 4 framing = 1
107 spread = 10
0x102 pattern = 1
0x102 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 11
0x207 Lane23AdjustRequest = 11
0x103 VS set = 1 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x103 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 11
0x203 Lane23Status = 11
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x102 pattern = 3
0x102 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 400
0x202 Lane01Status = 77
0x203 Lane23Status = 77
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
102 pattern = 0
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] Driver supports precise vblank timestamp query.
[drm] kiq ring mec 2 pipe 1 q 0
[drm] VCN decode and encode initialized successfully(under DPG Mode).
[drm] JPEG decode initialized successfully.
amdgpufb0 at amdgpu0
amdgpu0: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
amdgpu0: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
amdgpu0: ring comp_1.0.0 uses VM inv eng 4 on hub 0
amdgpu0: ring comp_1.1.0 uses VM inv eng 5 on hub 0
amdgpu0: ring comp_1.2.0 uses VM inv eng 6 on hub 0
amdgpu0: ring comp_1.3.0 uses VM inv eng 7 on hub 0
amdgpu0: ring comp_1.0.1 uses VM inv eng 8 on hub 0
amdgpu0: ring comp_1.1.1 uses VM inv eng 9 on hub 0
amdgpu0: ring comp_1.2.1 uses VM inv eng 10 on hub 0
amdgpu0: ring comp_1.3.1 uses VM inv eng 11 on hub 0
amdgpu0: ring kiq_2.1.0 uses VM inv eng 12 on hub 0
amdgpu0: ring sdma0 uses VM inv eng 13 on hub 0
amdgpu0: ring sdma1 uses VM inv eng 14 on hub 0
amdgpu0: ring vcn_dec uses VM inv eng 0 on hub 1
amdgpu0: ring vcn_enc0 uses VM inv eng 1 on hub 1
amdgpu0: ring vcn_enc1 uses VM inv eng 4 on hub 1
amdgpu0: ring jpeg_dec uses VM inv eng 5 on hub 1
[drm] Initialized amdgpu 3.36.0 20150101 for amdgpu0 on minor 0
amdgpufb0: framebuffer at 0xd04c9000, size 2560×1440, depth 32, stride 10240
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:2560 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:2560 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:1280 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:1280 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:2560 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:1280 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 20, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 21, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 22, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 23, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 24, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 25, colorDepth = 0
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =10646
HW register value = 0x214
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =10239
HW register value = 0x1ff
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =17546
HW register value = 0x36d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =15475
HW register value = 0x305
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =17139
HW register value = 0x358
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =15068
HW register value = 0x2f1
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =40646
HW register value = 0x7f0

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =40239
HW register value = 0x7db

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =38989
HW register value = 0x79d

[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 1
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 37 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 37 data: 131073
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 40 data: 117901057
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 41 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 42 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 43 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 44 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 45 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 46 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 47 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 49 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 50 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 51 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 53 data: 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 56 data: 1
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 56 data: 1
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 58 data: 913509922
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 59 data: 13
[HW_AUDIO]:
AUDIO:az_configure: index: 2 data, 0xd, displayName OMEN 27i IPS:
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 60 data: 1431864734
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 61 data: 228103241
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 62 data: 1313164623
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 63 data: 1765224992
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 64 data: 1397770528
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 65 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 66 data: 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 17
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 16
[BIOS]:set_pixel_clock_v7:program display clock = 6969600, tg = 0, pll = 11, colorDepth = 0
[BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 54000
100 rate = 14
101 lane = 4 framing = 1
107 spread = 10
0x102 pattern = 1
0x102 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 11
0x207 Lane23AdjustRequest = 11
0x103 VS set = 1 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x103 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 11
0x203 Lane23Status = 11
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x102 pattern = 3
0x102 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 400
0x202 Lane01Status = 77
0x203 Lane23Status = 77
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
102 pattern = 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 2147483649
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 2147483648
[HW_AUDIO]:
========= AUDIO:dce_aud_az_enable: index: 2 data: 0x80000000
[HDCP_TOP]:
[HDCP_TOP]:[Link 0] mod_hdcp_add_display display 1[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =10646
HW register value = 0x214
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =10239
HW register value = 0x1ff
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =17546
HW register value = 0x36d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =15475
HW register value = 0x305
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =17139
HW register value = 0x358
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =15068
HW register value = 0x2f1
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =40646
HW register value = 0x7f0

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =40239
HW register value = 0x7db

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =40646
HW register value = 0x7f0

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =40239
HW register value = 0x7db

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:Current: dispclk_khz:707449 max_dppclk_khz:350222 dcfclk_khz:506000
dcfclk_deep_sleep_khz:43560 fclk_khz:506000 socclk_khz:506000
[BANDWIDTH_CALCS]:Calculated: dispclk_khz:707449 max_dppclk_khz:350222 dcfclk_khz:506000
dcfclk_deep_sleep_khz:43560 fclk_khz:506000 socclk_khz:506000
wsdisplay0 at amdgpufb0 kbdmux 1: console (default, vt100 emulation), using wskbd0
wsmux1: connecting to wsdisplay0
wskbd1: connecting to wsdisplay0
{drm:netbsd:gfx_v10_0_ring_test_ib+0x179} ERROR amdgpu: IB test timed out.
amdgpu0 {drm:netbsd:amdgpu_ib_ring_tests+0xdf} ERROR IB test failed on kiq_2.1.0 (-60).
{drm:netbsd:linux_workqueue_thread+0x15e} ERROR ib ring test failed (-60).
aq0: link is UP: speed=10000
[HDCP_TOP]:[Link 0] add display 1wsdisplay0: screen 1 added (default, vt100 emulation)
wsdisplay0: screen 2 added (default, vt100 emulation)
wsdisplay0: screen 3 added (default, vt100 emulation)
wsdisplay0: screen 4 added (default, vt100 emulation)

NetBSD

NetBSD 10 RC6

2024-03-18 vezhlys

NetBSD 10 is really close to final release now, the 6th release candidate was prepared on 12th of March, 2024. Last few RC releases were mainly focusing on security and minor fixes. Currently release is scheduled by the end of March, however the date is not set in stone and one or more release candidates can be prepared.

The formal release announcement is available here and should be updated for the any interim RC releases, including the final one in the same link. It took more than a year after netbsd-10 was branched to reach first RC release and few months passed after that. Not everything is perfect, a new DRM/KMS subsystem version supports more hardware, but also may lead to failures where it worked before. Supported graphics card may have different issues as well. Hopefully, they will be addressed in the future releases. However, the release brings strong performance improvements, plenty of new hardware support and device drivers, improvements to modern and legacy/vintage systems, new features and enhancements, multiple updates to third-party software and much more. Please test it! Download links for multiple platforms are available in the official blog post, more images can be explored from the CDN . And please report bugs here.

NetBSD

Booting NetBSD on HP 620LX

2023-10-14 vezhlys

Few weeks ago I got an opportunity to buy HP 620LX handheld PC. It is a small device based on Hitachi SH7709 SH-3 ~75MHz SoC with 16MB RAM, one CompactFlash slot and one CardBus (PCMCIA) slot. It also has an option to connect serial cable (cable comes with the device). The default operating system is Windows CE 2.0 (or 2.11 if you are lucky to find the ROM upgrade).

System was untested and didn’t have original power adapter, however was packaged in original box with most accessories available. Fortunately, the system booted successfully using 12V 1A adapter (the original adapter provides 2A if I am not mistaken), giving me an opportunity to test NetBSD on it. HP 620LX is supported by hpcsh port, which aims to run on various handheld devices based on SH-3/4 SoCs.

Installation process is not completely trivial on this type of devices. One important point is that booting NetBSD will completely reset Windows CE device, loosing all configuration and data, thus backup is required, if it contains something important to the user (not in my case). There’s no sysinst(8) support, CF memory card should be prepared in advance on another NetBSD system. The instructions are available here, even more detailed instructions can be found here (thanks @uwe for pointing this document in the mailing list). To make the long story short: two partitions should be prepared: one DOS partition of the “small” size (20-30MB), and at least one FFS partition for NetBSD root partition. The DOS partition needs to include kernel file and a boot loader application. Distribution sets should be extracted to the NetBSD partition(s) (at least base, etc IMHO), and initial configuration can be done for /etc/rc.conf, /etc/fstab, etc.

Once everything is ready, hpcboot.exe needs to be executed from Windows CE. Choosing the right bootloader executable appeared to be the first challenge though. Installation directory in the port’s distribution contains sh3-hpcboot.exe and sh4-hpcboot.exe with seemingly the obvious choice for SH-3 based device. The caveat is that the binary is build for Windows CE 2.11 and above, and it fails to run on Windows CE 2.0. My initial fear was that I would need to build one myself with the right tools. Fortunately, I found one in the NetBSD code instead. It is uuencoded, thus should be decoded first by running command uudecode -o hpcboot.exe hpcboot200.exe.uue. The bootloader program allows to choose the device and several boot flags, and after few seconds NetBSD boot messages appear on the screen. On initial boot I faced the second issue, related to disk labels. The main reason was that my FFS partition was not labeled as wd0a. It appeared to be an easy fix sudo disklabel -e /dev/rsd3 (rsd3 may differ on your device) and just edit and save label from f->a (in my case) in the opened editor. Soon after I had a properly booting system and could successfully login to the system. Here the final configuration can be performed, like creation of users, setting the passwords, etc.

What’s next? First of all, I plan to add hpc200.exe to distribution files. After, I would like to enable some of my pcmcia devices (wifi card and SATA card), test network, test serial, and just to keep port a little bit more alive! Time will tell.

Enjoy dmesg below for now:

NetBSD 10.99.9 on HP 620LX

NetBSD 10.99.9 (GENERIC) #0: Wed Oct 4 07:51:36 UTC 2023
mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/hpcsh/compile/GENERIC
HP 620LX
total memory = 16384 KB
avail memory = 12896 KB
timecounter: Timecounters tick every 15.625 msec
mainbus0 (root)
cpu0 at mainbus0: SH3 73.728 MHz PCLOCK 18.432 MHz
cpu0: 16KB/16B 4-way set-associative I/D-unified cache.
cpu0: U0, P0, P3 write-back; P1 write-through
cpu0: 4-way set-associative 128 TLB entries
cpu0: VPN mode, multiple virtual storage mode
btnmgr0 at mainbus0
wskbd2 at btnmgr0 mux 1
shb0 at mainbus0
rtc0 at shb0
scif0 at shb0
adc0 at shb0
j6x0tp0 at adc0
wsmouse0 at j6x0tp0 mux 0
wskbd1 at j6x0tp0 mux 1
j6x0lcd0 at shb0: brightness 21, contrast 21
hd64461if0 at shb0
hd64461video0 at hd64461if0: frame buffer = 512 KB , console
hpcfb0 at hd64461video0: 640×240 pixels, 256 colors, 80×24 chars
wsdisplay0 at hpcfb0 kbdmux 1: console (std, vt100 emulation)
wsmux1: connecting to wsdisplay0
wskbd2: connecting to wsdisplay0
wskbd1: connecting to wsdisplay0
hpcfb: 640×240 pixels, 256 colors, 80×24 chars
hpcfb: 640×240 pixels, 256 colors, 80×24 chars
hpcfb: 640×240 pixels, 256 colors, 80×24 chars
wsdisplay0: screen 1-3 added (std, vt100 emulation)
hd64461pcmcia0 at hd64461if0
com0 at hd64461if0autoconfiguration error: : device problem. don’t attach.
pfckbd0 at mainbus0
hpckbd0 at pfckbd0
wskbd0 at hpckbd0: console keyboard, using wsdisplay0
hpcapm0 at mainbus0: pseudo power management module
apmdev0 at hpcapm0: Power Management spec V1.2
timecounter: Timecounter “tmu_pclock_4” frequency 4608075 Hz quality 0
timecounter: Timecounter “clockinterrupt” frequency 64 Hz quality 0
pcmcia0 at hd64461pcmcia0
pcmcia1 at hd64461pcmcia0
wdc0 at pcmcia1 function 0:
wdc0: memory mapped mode
WARNING: system needs entropy for security; see entropy(7)
atabus0 at wdc0 channel 0
wd0 at atabus0 drive 0
wd0:
wd0: drive supports 1-sector PIO transfers, LBA addressing
wd0: 488 MB, 993 cyl, 16 head, 63 sec, 512 bytes/sect x 1000944 sectors
wd0: 32-bit data port
swwdog0: software watchdog initialized
WARNING: 1 error while detecting hardware; check system log.
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
kern.module.path=/stand/hpcsh/10.99.9/modules
entropy: best effort

Adding VT8261 support

Improved VX800 support

VIA V-RAID improvements

VT8237S UDMA mode fix

VT6415 IDE support implementation

Bringing up RAID Mode on VX900

VT8251 IDE/RAID mode functionality

VT6410 add-in cards and missing enable bits

Final notes

Initial analysis

Kernel debugging

BIOS bootloader

Conclusion

ZFS setup

Link aggregation

Samba setup

NFS setup

Other notes

Personal NetBSD blog