All posts by vezhlys

NetBSD 9.4 and 8.3

Around a month after the major NetBSD 10.0 release, two feature releases followed for the NetBSD 9 and 8 release branches. NetBSD 9.4 was formally released on 20th of April, 2024 and contains pretty big number of various improvements, bug and security fixes accumulated in almost two years. NetBSD 8.3 was released on 4th of May, 2024 and concluded the support for this release branch, no more bug or security fixes will be applied to it, pkgsrc also dropped support for it long ago, thus it is recommended to use later major releases (NetBSD 9 or 10). Nevertheless, it also contains quite a lot of changes since last 8.2 version was released around 4 years ago. It even contains a fix for the vte(4) driver bug which I was hunting for the several years. If there’s some reason you can’t use NetBSD 10.0, it is recommended to upgrade to the latest feature branches at least, preferably NetBSD 9.3.

NetBSD NAS software setup

Once boot process was solved, I needed to setup ZFS for my hard drives and several services like NFS and Samba, setup network bonding using the new dedicated lagg(4) interface with LACP protocol, which in turn would complete the major NAS functionality.

ZFS setup

Initial ZFS setup was pretty easy. Luckily, configuring ZFS modules (solaris, zfs) in modules.conf(5) file was enough to make it work, even if configuration file was located in chrooted root partition. I mainly followed the Creating ZFS pools on NetBSD article from the UnitedBSD , or more exactly the “Create a ZFS pool” section by creating a ZFS pool and datasets with the mount points. After that, adding “zfs=YES” line in rc.conf(5) file does the final trick in order to mount ZFS partitions in their intended locations. I also enabled de-duplication and gzip compression features. The main mistake followed after adding a second hard drive to the zpool, which was intended to be a mirrored drive, for which attach command should have been used. NetBSD’s zpool command doesn’t allow removal of the drive without proper redundancy and doesn’t support forced removal, thus I need to recreate the pool, which was a bit of painful setback. According to recommendations I scheduled once a month zpool scrub operation, but still need to setup scheduled snapshots in the nearest future.

Link aggregation

As mentioned previously QNAP TVS-675 system contains two expansion card slots using PCIe Gen3 x4 interface. Thanks to the cut at the back of the port, cards with x8 physical slot can also fit into the port (longer cards may not fit though without modifications, metal frame can block the insertion). The challenge in doing so that it was a very short distance between PSU and a slot bracket, which made it very difficult to unscrew it without removing the PSU first. Once the network card was physically in place, the major problem occurred while setting up the lagg(4) interface using link aggregation control protocol (LACP). It appeared that mcx(4) driver wasn’t setting up full-duplex data transmission required by the protocol. Fortunately, the fix was relatively easy and made it into NetBSD 10 release by enforcing full-duplex in the driver. Additionally, missing lagg parameters were documented in ifconfig(8) man page. After the fix, network bonding setup was pretty straightforward by creating /etc/ifconfig.lagg0 file:

create
laggproto lacp laggport mcx0 laggport mcx1
up

I also created ifconfig.mcx0 and ifconfig.mcx1 with only up command and added net_interfaces=”mcx0,mcx1,lagg0″ line to /etc/rc.conf to control initialization order and ensure that mcx interfaces are up before lagg0 interface is created and initialized. For dhcpcd I added dhcpcd_flags=”-qM lagg0″ flags. After reboot my switch was happy to accept link aggregation with my NAS system.

Samba setup

Next step was to install and enable samba(8). The small issue was the missing xbase set required by the samba installation, since I was not aware of this requirement. I simply downloaded the required set and extracted it manually. Other than that I could mainly reuse configuration file from Linux system by only adjusting required paths and placing it in /usr/pkg/etc/samba/smb.conf location. Of course I needed to create a samba user (smbpasswd). Also worth to note that smbd, nmbd and winbindd services should be enabled instead of samba service, contrary to typical Linux experience.

NFS setup

NFS configuration was not compatible with the Linux one on the other hand and I needed to rewrite it from scratch. NetBSD “how to set up nfs and nis” and UnitedBSD NFS on NetBSD: server and client side wiki articles were a great guidance. To enable NFS properly I needed to add these line to /etc/rc.conf:

# NFS server
rpcbind=YES
nfs_server=YES
nfsd_flags=’-n8′
mountd=${nfs_server}
lockd=${nfs_server}
statd=${nfs_server}

And configure /etc/exports according to examples from the articles above. From client side I just needed to adjust /etc/fstab to the new NFS path.

Other notes

I also installed rtorrent as my torrent service and utilized cron to enable it after boot by adding this line to crontab configuration:

@reboot /usr/bin/tmux new-session -d '/usr/pkg/bin/rtorrent -D -I -n -o import=$
PWD/.rtorrent.rc'

.rtorrent.rc file just need to point to the session path, otherwise I kept it standard. After that tmux attach -d -t 0 command can be used to attach to the rtorrent session and CTRL+B D to detach from it.

In order to monitor HDD and its temperature I installed smartmontools utility. Current temperature can be retrieved using sudo smartctl -a /dev/rwd1|grep -i temp command (raw device should be used, thus rwd1 instead of wd1).

Finally I created the patch for the CPU temperature which didn’t make it to NetBSD 10 release, but hopefully will be available with NetBSD 10.1 through envstat(8) command. For time being I am using the patched kernel.

Overall my experience is quite positive with the new setup. There are still few improvements required, mainly for the data redundancy and potentially better power management and improved CPU support. The NAS device doesn’t like enclosed environments without proper airflow and my become extremely noisy in such case, however it works pretty silently be default. Actually the main noise was coming from 10-Gbit ethernet card, which has an active fan. Hard drives are also pretty audible unfortunately, thus SSDs would be preferred if silence is the priority.

Boot into SSD in QNAP TVS-675

Historically, my first NAS system was running NetBSD operating system (5th release if I am not mistaken), however after a hardware update, I was forced to switch to the Debian Linux due to hardware support issues at that time. Since then I have used few different distributions for over a decade (mainly Arch and Artix). Several years ago I upgraded the underlying platform again with the hopes to use it for at least as long as my previous system. This NAS setup is based on Biostar FX9830M motherboard. My goal in doing so is to make setup as cheap as possible by scrapping various parts from my closet. Unfortunately, it didn’t workout as planned, mainly due to uncomfortably noisy operation of aforementioned motherboad’s CPU fan, which I have never managed to remedy (unusual fan connector and cooling solution is a limiting factor, requiring to do custom solutions without knowing if that solution will work). In addition, the compact case didn’t provide enough airflow leading to slightly overheating HDDs which may affect their operational lifetime. Thus, I decided that it may be a good chance to come back to a long time dream of switching back to NetBSD in my NAS setup and I acquired QNAP TVS-675 NAS system for this purpose.

Under the hood it uses Zhaoxin KaiXian KX-U6580 8-core x86-64 CPU, has 6 HDD bays, has an option to add two PCIe Gen 3 x4 cards (the slot allows to attach longer cards thanks to the cut at the back of it), and supports NVMe expansion slots. It is almost a typical x86-64 PC, just wrapped into a “fancy” case specifically designed for NAS purposes. It operates pretty silently by default, with only audible noise coming from HDDs themselves during heavy operations (once high capacity SSDs are cheap enough I may switch to them).

The installation of the NetBSD 10.0 didn’t bring any surprises and went smoothly, however I faced the first issue just after the first reboot. There was no support to boot directly from SATA SSD (limitation of the system’s BIOS). Only the USB boot devices are supported. As a result, I started to look into options somehow to start booting from USB, to switch the root system to the SSD partition at the subsequent stages of the boot process. After reading a few resources (will mention them at the end of the article) and consulting the NetBSD developers, I decided to use a pretty simple approach with SSD root partition being mounted to /altroot, where kernel eventually is being instructed to chroot to it. The approach is similar – to root on ZFS or CGD functionality, however I didn’t configure a separate ramdisk for that, at least now.

In order to achieve that, I needed to prepare a bootable USB flash drive. One can use a lengthy instructions with the UEFI in mind, or install a minimal system using installation media, however I took a lazy approach by dissecting provided installation media itself. I just mounted it on my main NetBSD system and deleted all unnecessary folders and files, updated netbsd kernel (I am building a custom one, but GENERIC can be used) and updated /etc/rc script by mounting required partitions, including SSD root to /altroot and finally setting init.root kernel option to /altroot, so that it would switch to it during boot process:

PATH=/sbin:/bin
export PATH

mount -u /
mount -t tmpfs tmpfs /tmp
mount /altroot
sysctl -w init.root=/altroot

# done, move on to multiuser mode
exit 0

To complete a setup, I added required fields to /etc/fstab by setting correct /altroot mount point to the SSD’s root partition.

NAME=<usbpartionid>		/		ffs	rw		1 1
tmpfs			/tmp		tmpfs	rw		0 0
NAME=<ssdpartitionid>			/altroot	ffs	ro,log	1 1

The important part was to mount /altroot as read-only (ro), otherwise automatic filesystem check kicked-in and disrupted the boot process (it can’t check rw mounted partitions), requiring for the manual interaction. It is not an issue, since root partition will remount in rw mode by reading SSDs /etc/fstab. If there’s a need to change some files in /altroot before chroot (like rndseed for example), automount can be still rw but rc script should remount /altroot manually as read only shortly before sysctl command. Alternative approach may be to skip remounting root partition at all, but I haven’t tried it.

After reboot the system successfully booted and switched to SSD root folder!

Ideally I would like to avoid having USB flash drive being attached at all. I believe that integrated USB DISK module can be utilized somehow, but I haven’t explored that just yet, since i I don’t want to mess up the default boot configuration for the their own custom OS and it needs more time and skills to implement. For the time being, I would likely buy a very short USB flash driver, similar to Intenso Slim Line to make protrusion from the case as minimal as it can be.

The next step will be to setup my hard drives to using ZFS file system, setup NFS and samba as well as network with lagg(4) link aggregation. I am unsure at the moment, where I should load zfs modules, should it be before the chroot operation happens or it can be loaded after. Currently I am utilizing SSD root partition’s /etc/modules.conf file, which loads modules correctly, however I am not certain if it won’t be too late for mounting ZFS partitions automatically. I will definitely explore that in the next post.

Few useful resources on this topic:
HowTo: Making a bootable ISO w/ miniroot.kmod etc.
Building a NetBSD ramdisk kernel
Root On ZFS
NetBSD Full-Disk Encryption with CGD
Building NetBSD system components

NetBSD 10.0 released!

After years of development NetBSD 10 reached the finish line and the final 10.0 release was officially announced yesterday. It brings multiple improvements, updates and new features in the all areas of the system, being it performance improvements, hardware support, security, virtualization, networking stack, storage or applications and APIs. Please check release announcement and CHANGES for the more details. The release announcement doesn’t mention experimental igc(4) driver for Intel I225/I226 2.5G Ethernet adapters. I have those on one of my systems and can confirm that they work in at least simple setup. The important update was a DRM sync with Linux 5.6. Unfortunately, it didn’t go smoothly, multiple issues remain with graphics support with plans to improve it in the future releases. From my personal experience I can currently use Radeon RX5700XT with some caveats, which wasn’t even supported in previous releases.

Personally for me this release is quite important in few ways, it is the first major release since I officially became a developer myself and it brings important updates to hardware I use or plan to utilize in near future like lagg(4) link aggregation interface with mcx(4) 10Gbit controller or above mentioned RX5700XT and igc(4) support. I can’t say my own contributions were important (few bug and build fixes, and tons of spelling fixes in documentation, log messages and comments), however I believe I invested considerably more time into this release than any other previous one in some less direct ways like reporting, testing and facilitating bug fixes. Few last minute fixes were directly related to my bug reports.

The release can be downloaded from CDN service or any other project mirrors. Please don’t hesitate to try it and report bugs! As usual, it is strongly recommended to update for users of earlier NetBSD releases.

Full dmesg below:

NetBSD 10.0 on Ryzen 5600/Gigabyte A520 Aorus Elite/Radeon RX5700XT

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013,
2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023,
2024
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.

NetBSD 10.0 (GENERIC_AMDGPU) #8: Sun Mar 31 22:50:50 EEST 2024
andriusv@agraphic-pc:/home/andriusv/obj/sys/arch/amd64/compile/GENERIC_AMDGPU
total memory = 32691 MB
avail memory = 31592 MB
timecounter: Timecounters tick every 10.000 msec
Kernelized RAIDframe activated
RTC BIOS diagnostic error 0xf
timecounter: Timecounter “i8254” frequency 1193182 Hz quality 100
efi: systbl at pa bdb74018
mainbus0 (root)
ACPI: RSDP 0x00000000BCEBD014 000024 (v02 ALASKA)
ACPI: XSDT 0x00000000BCEBC728 0000EC (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: FACP 0x00000000BC7D8000 000114 (v06 ALASKA A M I 01072009 AMI 00010013)
ACPI: DSDT 0x00000000BC6CF000 0069DC (v02 ALASKA A M I 01072009 INTL 20190509)
ACPI: FACS 0x00000000BCEB7000 000040
ACPI: SSDT 0x00000000BC7E7000 00AFB8 (v02 GBT GSWApp 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC7DE000 008CE9 (v02 AMD AmdTable 00000002 MSFT 04000000)
ACPI: SSDT 0x00000000BC7DA000 003D7C (v02 AMD AMD AOD 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC7D9000 0001AD (v02 ALASKA CPUSSDT 01072009 AMI 01072009)
ACPI: FIDT 0x00000000BC7D1000 00009C (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: MCFG 0x00000000BC7D0000 00003C (v01 ALASKA A M I 01072009 MSFT 00010013)
ACPI: HPET 0x00000000BC7CF000 000038 (v01 ALASKA A M I 01072009 AMI 00000005)
ACPI: IVRS 0x00000000BC7CE000 0000D0 (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: FPDT 0x00000000BC7CD000 000044 (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: BGRT 0x00000000BC7CC000 000038 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: TPM2 0x00000000BC7CB000 00004C (v04 ALASKA A M I 00000001 AMI 00000000)
ACPI: PCCT 0x00000000BC7CA000 00006E (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: SSDT 0x00000000BC7C6000 0030FB (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: CRAT 0x00000000BC7C5000 000B90 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: CDIT 0x00000000BC7C4000 000029 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: WPBT 0x00000000BC6E0000 000038 (v01 ALASKA A M I 00000001 GBT 20181220)
ACPI: SSDT 0x00000000BC6DF000 00068E (v02 AMD ArticDGP 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC6DD000 001522 (v02 AMD ArticTPX 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC6DC000 000788 (v02 AMD ArticNOI 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC6D8000 003A23 (v02 AMD ArticN 00000001 INTL 20190509)
ACPI: WSMT 0x00000000BC6D7000 000028 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: APIC 0x00000000BC6D6000 00015E (v04 ALASKA A M I 01072009 AMI 00010013)
ACPI: SSDT 0x00000000BC7D6000 00147F (v02 AMD ArticC 00000001 INTL 20190509)
ACPI: SSDT 0x00000000BC7D5000 0000BF (v01 AMD AmdTable 00001000 INTL 20190509)
ACPI: 12 ACPI AML tables successfully acquired and loaded
ioapic0 at mainbus0 apid 13: pa 0xfec00000, version 0x21, 24 pins
ioapic1 at mainbus0 apid 14: pa 0xfec01000, version 0x21, 32 pins
cpu0 at mainbus0 apid 0
cpu0: Use mfence to serialize rdtsc
cpu0: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu0: node 0, package 0, core 0, smt 0
cpu0: SVM disabled by the BIOS
cpu1 at mainbus0 apid 2
cpu1: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu1: node 0, package 0, core 1, smt 0
cpu2 at mainbus0 apid 4
cpu2: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu2: node 0, package 0, core 2, smt 0
cpu3 at mainbus0 apid 6
cpu3: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu3: node 0, package 0, core 3, smt 0
cpu4 at mainbus0 apid 8
cpu4: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu4: node 0, package 0, core 4, smt 0
cpu5 at mainbus0 apid 10
cpu5: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu5: node 0, package 0, core 5, smt 0
cpu6 at mainbus0 apid 1
cpu6: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu6: node 0, package 0, core 0, smt 1
cpu7 at mainbus0 apid 3
cpu7: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu7: node 0, package 0, core 1, smt 1
cpu8 at mainbus0 apid 5
cpu8: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu8: node 0, package 0, core 2, smt 1
cpu9 at mainbus0 apid 7
cpu9: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu9: node 0, package 0, core 3, smt 1
cpu10 at mainbus0 apid 9
cpu10: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu10: node 0, package 0, core 4, smt 1
cpu11 at mainbus0 apid 11
cpu11: AMD Ryzen 5 5600 6-Core Processor , id 0xa20f12
cpu11: node 0, package 0, core 5, smt 1
acpi0 at mainbus0: Intel ACPICA 20221020
acpi0: X/RSDT: OemId , AslId
acpi0: autoconfiguration error: invalid PCI address for D003
acpi0: autoconfiguration error: invalid PCI address for D00A
acpi0: MCFG: segment 0, bus 0-127, address 0x00000000f0000000
acpi0: SCI interrupting at int 9
acpi0: fixed power button present
timecounter: Timecounter “ACPI-Safe” frequency 3579545 Hz quality 900
hpet0 at acpi0: high precision event timer (mem 0xfed00000-0xfed00400)
timecounter: Timecounter “hpet0” frequency 14318180 Hz quality 2000
AMDN (PNP0C01) at acpi0 not configured
attimer1 at acpi0 (TMR, PNP0100): io 0x40-0x43 irq 0
pcppi1 at acpi0 (SPKR, PNP0800): io 0x61
spkr0 at pcppi1: PC Speaker
wsbell at spkr0 not configured
midi0 at pcppi1: PC speaker
sysbeep0 at pcppi1
com0 at acpi0 (UAR1, PNP0501-0): io 0x3f8-0x3ff irq 4
com0: ns16550a, 16-byte FIFO
acpibut0 at acpi0 (PWRB, PNP0C0C-170): ACPI Power Button
GPIO (AMDI0030) at acpi0 not configured
TPM (MSFT0101) at acpi0 not configured
PTIO (AMDIF030) at acpi0 not configured
acpitz0 at acpi0 (TZ10)
acpitz0: levels: critical 20.8 C, hot 19.8 C, passive 16.8 C, passive cooling
acpitz1 at acpi0 (UAD0)
acpitz1: levels: critical 20.8 C, hot 19.8 C, passive 16.8 C, passive cooling
acpiwmi0 at acpi0 (GSA1, PNP0C14-GSADEV0): ACPI WMI Interface
acpiwmibus at acpiwmi0 not configured
acpiwmi1 at acpi0 (AOD, PNP0C14-AOD): ACPI WMI Interface
acpiwmibus at acpiwmi1 not configured
ACPI: Enabled 1 GPEs in block 00 to 1F
attimer1: attached to pcppi1
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
amdsmn0 at pci0 dev 0 function 0: AMD System Management Network
amdzentemp0 at amdsmn0: AMD CPU Temperature Sensors (Family19h)
AMD Family17h/7xh IOMMU (IOMMU system) at pci0 dev 0 function 2 not configured
pchb0 at pci0 dev 1 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb0 at pci0 dev 1 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb0: PCI Express capability version 2 x4 @ 8.0GT/s
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
nvme0 at pci1 dev 0 function 0: Western Digital (SanDisk) product 5019 (rev. 0x01)
nvme0: NVMe 1.4
nvme0: for admin queue interrupting at msix0 vec 0
nvme0: WDC WDS100T2B0C-00PXH0, firmware 233010WD, serial 21281W452002
nvme0: for io queue 1 interrupting at msix0 vec 1 affinity to cpu0
nvme0: for io queue 2 interrupting at msix0 vec 2 affinity to cpu1
nvme0: for io queue 3 interrupting at msix0 vec 3 affinity to cpu2
nvme0: for io queue 4 interrupting at msix0 vec 4 affinity to cpu3
nvme0: for io queue 5 interrupting at msix0 vec 5 affinity to cpu4
nvme0: for io queue 6 interrupting at msix0 vec 6 affinity to cpu5
nvme0: for io queue 7 interrupting at msix0 vec 7 affinity to cpu6
nvme0: for io queue 8 interrupting at msix0 vec 8 affinity to cpu7
nvme0: for io queue 9 interrupting at msix0 vec 9 affinity to cpu8
nvme0: for io queue 10 interrupting at msix0 vec 10 affinity to cpu9
nvme0: for io queue 11 interrupting at msix0 vec 11 affinity to cpu10
nvme0: for io queue 12 interrupting at msix0 vec 12 affinity to cpu11
ld0 at nvme0 nsid 1
ld0: 931 GB, 121601 cyl, 255 head, 63 sec, 512 bytes/sect x 1953525168 sectors
ppb1 at pci0 dev 1 function 2: AMD 17h/7xh PCIe (rev. 0x00)
ppb1: PCI Express capability version 2 x8 @ 8.0GT/s
ppb1: link is x4 @ 8.0GT/s
pci2 at ppb1 bus 2
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
xhci0 at pci2 dev 0 function 0: AMD product 43ec (rev. 0x00)
xhci0: 64-bit DMA
xhci0: interrupting at msix1 vec 0
xhci0: xHCI version 1.10
usb0 at xhci0: USB revision 3.1
usb1 at xhci0: USB revision 2.0
ahcisata0 at pci2 dev 0 function 1: AMD 500 Series AHCI (rev. 0x00)
ahcisata0: 64-bit DMA
ahcisata0: AHCI revision 1.31, 6 ports, 32 slots, CAP 0xef36ff25
ahcisata0: interrupting at msi2 vec 0
atabus0 at ahcisata0 channel 0
atabus1 at ahcisata0 channel 1
atabus2 at ahcisata0 channel 4
atabus3 at ahcisata0 channel 5
ppb2 at pci2 dev 0 function 2: AMD 500 Series PCIe (rev. 0x00)
ppb2: PCI Express capability version 2
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled, rd/line, wr/inv ok
ppb3 at pci3 dev 0 function 0: AMD 500 Series PCIe (rev. 0x00)
ppb3: PCI Express capability version 2 x2 @ 8.0GT/s
pci4 at ppb3 bus 4
pci4: i/o space, memory space enabled, rd/line, wr/inv ok
aq0 at pci4 dev 0 function 0: Aquantia AQC100 10 Gigabit Network Adapter (rev. 0x02)
aq0: Atlantic revision B1, F/W version 3.1.58
aq0: fw2x> F/W capabilities=0x63c0001900007f20
aq0: Etheraddr: [_MAC_XXXXXXXXXX]
pchb1 at pci0 dev 2 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb2 at pci0 dev 3 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb4 at pci0 dev 3 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb4: PCI Express capability version 2 x16 @ 8.0GT/s
pci5 at ppb4 bus 5
pci5: i/o space, memory space enabled, rd/line, wr/inv ok
ppb5 at pci5 dev 0 function 0: ATI Technologies product 1478 (rev. 0xc1)
ppb5: PCI Express capability version 2
pci6 at ppb5 bus 6
pci6: i/o space, memory space enabled, rd/line, wr/inv ok
ppb6 at pci6 dev 0 function 0: ATI Technologies product 1479 (rev. 0x00)
ppb6: PCI Express capability version 2 x16 @ 16.0GT/s
pci7 at ppb6 bus 7
pci7: i/o space, memory space enabled, rd/line, wr/inv ok
amdgpu0 at pci7 dev 0 function 0: ATI Technologies Radeon RX 5600 OEM/5600 XT / 5700/5700 XT (rev. 0xc1)
hdaudio0 at pci7 dev 0 function 1: HD Audio Controller
hdaudio0: interrupting at msi4 vec 0
hdaudio0: HDA ver. 1.0, OSS 6, ISS 0, BSS 0, SDO 1, 64-bit
hdafg0 at hdaudio0: ATI R6xx HDMI
hdafg0: HDMI00 2ch: Digital Out [Jack]
hdafg0: HDMI01 2ch: Digital Out [Jack]
hdafg0: HDMI02 2ch: Digital Out [Jack]
hdafg0: HDMI03 2ch: Digital Out [Jack]
hdafg0: HDMI04 2ch: Digital Out [Jack]
hdafg0: HDMI05 2ch: Digital Out [Jack]
hdafg0: 2ch/0ch 32000Hz 44100Hz 48000Hz PCM16 AC3
audio0 at hdafg0: playback
audio0: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
spkr1 at audio0: PC Speaker (synthesized)
wsbell at spkr1 not configured
pchb3 at pci0 dev 4 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb4 at pci0 dev 5 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb5 at pci0 dev 7 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb7 at pci0 dev 7 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb7: PCI Express capability version 2 x16 @ 16.0GT/s
pci8 at ppb7 bus 8
pci8: i/o space, memory space enabled, rd/line, wr/inv ok
AMD product 148a (non-essential instrumentation, subclass 0x00) at pci8 dev 0 function 0 not configured
pchb6 at pci0 dev 8 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb8 at pci0 dev 8 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb8: PCI Express capability version 2 x16 @ 16.0GT/s
pci9 at ppb8 bus 9
pci9: i/o space, memory space enabled, rd/line, wr/inv ok
AMD Family17h/7xh Reserved SPP (non-essential instrumentation, subclass 0x00) at pci9 dev 0 function 0 not configured
amdccp0 at pci9 dev 0 function 1: AMD Cryptographic Coprocessor
xhci1 at pci9 dev 0 function 3: AMD Family17h/7xh USB 3.0 Host Controller (rev. 0x00)
xhci1: 64-bit DMA
xhci1: interrupting at msix5 vec 0
xhci1: xHCI version 1.10
usb2 at xhci1: USB revision 3.1
usb3 at xhci1: USB revision 2.0
hdaudio1 at pci9 dev 0 function 4: HD Audio Controller
hdaudio1: interrupting at msi6 vec 0
hdaudio1: HDA ver. 1.0, OSS 4, ISS 4, BSS 0, SDO 1, 64-bit
hdafg1 at hdaudio1: Realtek product 0b00
hdafg1: DAC00 6ch: Speaker [Jack]
hdafg1: DAC01 2ch: HP Out [Jack]
hdafg1: DIG02 2ch: SPDIF Out [Jack]
hdafg1: ADC03 2ch: Line In [Jack], Mic In [Jack]
hdafg1: ADC04 2ch: Mic In [Jack]
hdafg1: 6ch/2ch 32000Hz 44100Hz 48000Hz 88200Hz 96000Hz 192000Hz PCM16 PCM20 PCM24 AC3
audio1 at hdafg1: playback, capture, full duplex, independent
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for recording
spkr2 at audio1: PC Speaker (synthesized)
wsbell at spkr2 not configured
piixpm0 at pci0 dev 20 function 0: AMD X370/X399 SMBus Controller (rev. 0x61)
piixpm0: interrupting at SMI,
iic0 at piixpm0 port 0: I2C bus
iic1 at piixpm0 port 1: I2C bus
pcib0 at pci0 dev 20 function 3: AMD FCH LPC (rev. 0x51)
pchb7 at pci0 dev 24 function 0: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb8 at pci0 dev 24 function 1: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb9 at pci0 dev 24 function 2: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb10 at pci0 dev 24 function 3: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb11 at pci0 dev 24 function 4: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb12 at pci0 dev 24 function 5: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb13 at pci0 dev 24 function 6: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb14 at pci0 dev 24 function 7: AMD 17h/7xh Data Fabric (rev. 0x00)
isa0 at pcib0
pckbc0 at isa0 port 0x60-0x64
acpicpu0 at cpu0: ACPI CPU
acpicpu0: C1: FFH, lat 1 us, pow 0 mW
acpicpu0: C2: I/O, lat 18 us, pow 0 mW
acpicpu0: P0: FFH, lat 1 us, pow 3850 mW, 3500 MHz
acpicpu0: P1: FFH, lat 1 us, pow 2800 mW, 2800 MHz
acpicpu0: P2: FFH, lat 1 us, pow 1980 mW, 2200 MHz
acpicpu1 at cpu1: ACPI CPU
acpicpu2 at cpu2: ACPI CPU
acpicpu3 at cpu3: ACPI CPU
acpicpu4 at cpu4: ACPI CPU
acpicpu5 at cpu5: ACPI CPU
acpicpu6 at cpu6: ACPI CPU
acpicpu7 at cpu7: ACPI CPU
acpicpu8 at cpu8: ACPI CPU
acpicpu9 at cpu9: ACPI CPU
acpicpu10 at cpu10: ACPI CPU
acpicpu11 at cpu11: ACPI CPU
timecounter: Timecounter “clockinterrupt” frequency 100 Hz quality 0
timecounter: Timecounter “TSC” frequency 3493442000 Hz quality 3000
uhub0 at usb0: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub0: 3 ports with 3 removable, self powered
uhub1 at usb1: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub1: 9 ports with 9 removable, self powered
uhub2 at usb2: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub2: 4 ports with 4 removable, self powered
uhub3 at usb3: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub3: 4 ports with 4 removable, self powered
ld0: GPT GUID: 9b94f472-237d-4601-b411-c7262ae07e17
dk0 at ld0: “17abe03b-7c17-44cc-8dac-d3d56968b6b1”, 262144 blocks at 2048, type: msdos
dk1 at ld0: “c072c1e3-5d0b-4bd4-8789-7370295360e1”, 134897664 blocks at 264192, type: ffs
dk2 at ld0: “0291617a-ffbb-457e-b908-af9f61e5790f”, 67010560 blocks at 135161856, type: swap
dk3 at ld0: “ca370a40-b6d3-4b0a-9270-00acc6df4e2b”, 419430400 blocks at 202172416, type: ffs
dk4 at ld0: “8ae92095-2b67-450a-b3ac-32c912b78f08”, 1331922319 blocks at 621602816, type: ffs
IPsec: Initialized Security Association Processing.
ahcisata0 port 0: device present, speed: 6.0Gb/s
ahcisata0 port 1: device present, speed: 1.5Gb/s
uhub4 at uhub1 port 3: Genesys Logic (0x05e3) USB2.0 Hub (0x0608), class 9/0, rev 2.00/60.90, addr 1
uhub4: single transaction translator
uhub4: 4 ports with 4 removable, self powered
uhub5 at uhub3 port 2: GenesysLogic (0x05e3) USB2.1 Hub (0x0610), class 9/0, rev 2.10/66.02, addr 1
uhub5: multiple transaction translators
uhub5: 3 ports with 2 removable, self powered
umass0 at uhub2 port 1 configuration 1 interface 0
umass0: Generic (0x21c4) USB Storage (0xb064), rev 3.20/0.09, addr 2
umass0: using SCSI over Bulk-Only
scsibus0 at umass0: 2 targets, 3 luns per target
sd0 at scsibus0 target 0 lun 0: disk removable
sd0: drive offline
autoconfiguration error: sd0: unable to open device, error = 19
sd1 at scsibus0 target 0 lun 1: disk removable
sd1: drive offline
autoconfiguration error: sd1: unable to open device, error = 19
sd2 at scsibus0 target 0 lun 2: disk removable
sd2: drive offline
autoconfiguration error: sd2: unable to open device, error = 19
uhub6 at uhub2 port 2: GenesysLogic (0x05e3) USB3.1 Hub (0x0620), class 9/0, rev 3.20/66.02, addr 3
uhub6: 2 ports with 2 removable, self powered
uhidev0 at uhub5 port 3 configuration 1 interface 1
uhidev0: ENE (0x0cf2) AGON3 Light FX Device (0x7750), rev 2.00/1.00, addr 4, iclass 3/0
uhidev0: 236 report ids
uhid0 at uhidev0 reportid 236: input=64, output=64, feature=0
ubt0 at uhub4 port 4
ubt0: Cambridge Silicon Radio (0x0a12) BT DONGLE10 (0x0001), rev 2.00/88.91, addr 2
wd0 at atabus0 drive 0
wd0:
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 223 GB, 465141 cyl, 16 head, 63 sec, 512 bytes/sect x 468862128 sectors
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133), WRITE DMA FUA, NCQ (32 tags)
wd0(ahcisata0:0:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA), NCQ (31 tags)
atapibus0 at atabus1: 1 targets
cd0 at atapibus0 drive 0: cdrom removable
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
cd0(ahcisata0:1:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100) (using DMA)
uhub7 at uhub3 port 3: VIA Labs, Inc. (0x2109) USB2.0 Hub (0x2817), class 9/0, rev 2.10/90.23, addr 5
uhub7: multiple transaction translators
uhub7: 4 ports with 4 removable, self powered
uhub8 at uhub2 port 3: VIA Labs, Inc. (0x2109) USB3.0 Hub (0x0817), class 9/0, rev 3.10/90.23, addr 6
uhub8: 4 ports with 4 removable, self powered
uhidev1 at uhub1 port 4 configuration 1 interface 0
uhidev1: ITE Tech. Inc. (0x048d) ITE Device (0x5702), rev 2.00/0.01, addr 3, iclass 3/0
uhidev1: 204 report ids
uhid1 at uhidev1 reportid 90: input=0, output=0, feature=16
uhid2 at uhidev1 reportid 204: input=0, output=0, feature=63
umass1 at uhub2 port 4 configuration 1 interface 0
umass1: StoreJet Transcend (0x174c) StoreJet Transcend (0x5106), rev 3.00/80.00, addr 7
umass1: using SCSI over Bulk-Only
scsibus1 at umass1: 2 targets, 1 lun per target
sd3 at scsibus1 target 0 lun 0: disk fixed
sd3: 238 GB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 500118192 sectors
uhub9 at uhub7 port 2: Genesys Logic (0x05e3) USB2.0 Hub (0x0608), class 9/0, rev 2.00/32.98, addr 8
uhub9: single transaction translator
uhub9: 4 ports with 4 removable, self powered
uhidev2 at uhub9 port 2 configuration 1 interface 0
uhidev2: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 9, iclass 3/1
ukbd0 at uhidev2
wskbd0 at ukbd0: console keyboard
uhidev3 at uhub9 port 2 configuration 1 interface 1
uhidev3: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 9, iclass 3/0
uhid3 at uhidev3: input=4, output=0, feature=0
uhidev4 at uhub9 port 2 configuration 1 interface 2
uhidev4: Fnatic Gear (0x195d) RUSH Mechanical Keyboard (0x2030), rev 2.00/1.09, addr 9, iclass 3/0
ukbd1 at uhidev4
wskbd1 at ukbd1 mux 1
uhidev5 at uhub7 port 3 configuration 1 interface 0
uhidev5: Kensington (0x047d) Orbit Fusion Wireless Trackball (0x807b), rev 1.10/10.01, addr 10, iclass 3/1
ums0 at uhidev5: 8 buttons, W and Z dirs
wsmouse0 at ums0 mux 0
uhidev6 at uhub7 port 3 configuration 1 interface 1
uhidev6: Kensington (0x047d) Orbit Fusion Wireless Trackball (0x807b), rev 1.10/10.01, addr 10, iclass 3/0
uhidev6: 1 report ids
uhid4 at uhidev6 reportid 1: input=2, output=0, feature=0
uhidev7 at uhub7 port 3 configuration 1 interface 2
uhidev7: Kensington (0x047d) Orbit Fusion Wireless Trackball (0x807b), rev 1.10/10.01, addr 10, iclass 3/0
uhid5 at uhidev7: input=16, output=16, feature=0
uaudio0 at uhub7 port 4 configuration 1 interface 0
uaudio0: C-Media Electronics Inc. (0x0d8c) Genesis Radium 100 (0x0014), rev 1.10/1.00, addr 11
uaudio0: audio rev 1.00
audio2 at uaudio0: playback, capture, full duplex, independent
audio2: slinear_le:16 2ch 48000Hz, blk 11520 bytes (60ms) for playback
audio2: slinear_le:16 1ch 48000Hz, blk 6000 bytes (62.5ms) for recording
spkr3 at audio2: PC Speaker (synthesized)
wsbell at spkr3 not configured
uhidev8 at uhub7 port 4 configuration 1 interface 3
uhidev8: C-Media Electronics Inc. (0x0d8c) Genesis Radium 100 (0x0014), rev 1.10/1.00, addr 11, iclass 3/0
uhid6 at uhidev8: input=4, output=4, feature=0
swwdog0: software watchdog initialized
WARNING: 5 errors while detecting hardware; check system log.
boot device: ld0
root on dk1 dumps on dk2
root file system type: ffs
kern.module.path=/stand/amd64/10.0/modules
[drm] initializing kernel modesetting (NAVI10 0x1002:0x731F 0x1DA2:0xE411 0xC1).
[drm] register mmio base: 0xFCA00000
[drm] register mmio size: 524288
[drm] set register base offset for ATHUB
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for CLKA
[drm] set register base offset for DF
[drm] set register base offset for DMU
[drm] set register base offset for GC
[drm] set register base offset for HDP
[drm] set register base offset for MMHUB
[drm] set register base offset for MP0
[drm] set register base offset for MP1
[drm] set register base offset for NBIF
[drm] set register base offset for NBIF
[drm] set register base offset for OSSSYS
[drm] set register base offset for SDMA0
[drm] set register base offset for SDMA1
[drm] set register base offset for SMUIO
[drm] set register base offset for THM
[drm] set register base offset for UVD
[drm] add ip block number 0
[drm] add ip block number 1
[drm] add ip block number 2
[drm] add ip block number 3
[drm] add ip block number 4
[drm] add ip block number 5
[drm] add ip block number 6
[drm] add ip block number 7
[drm] add ip block number 8
[drm] add ip block number 9
ATOM BIOS: 113-1E4112U-O45
[drm] VCN decode is enabled in VM mode
[drm] VCN encode is enabled in VM mode
[drm] JPEG decode is enabled in VM mode
[drm] vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit
amdgpu0: VRAM: 8176M 0x0000008000000000 – 0x00000081FEFFFFFF (8176M used)
amdgpu0: GART: 512M 0x0000000000000000 – 0x000000001FFFFFFF
[drm] Detected VRAM RAM=8176M, BAR=256M
[drm] RAM width 256bits GDDR6
Zone kernel: Available graphics memory: 9007199253296414 KiB
Zone dma32: Available graphics memory: 2097152 KiB
[drm] amdgpu: 8176M of VRAM memory ready
[drm] amdgpu: 8176M of GTT memory ready.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] PCIE GART of 512M enabled (table at 0x0000008000300000).
amdgpu0: interrupting at msi7 vec 0 (amdgpu0)
[drm] use_doorbell being set to: [true]
[drm] use_doorbell being set to: [true]
[drm] Found VCN firmware Version ENC: 1.14 DEC: 5 VEP: 0 Revision: 20
[drm] PSP loading VCN firmware
[drm] reserve 0x900000 from 0x81fe400000 for PSP TMR
amdgpu0: warn: RAS: ras ta ucode is not available
use vbios provided pptable
smu driver if version = 0x00000033, smu fw if version = 0x00000037, smu fw version = 0x002a4000 (42.64.0)
SMU driver if version not matched
OD: Gfxclk: (800, 2054)
OD: Gfx1: (800, 2858)
OD: Gfx2: (1427, 3267)
OD: Gfx3: (2054, 4780)
OD: UclkFmax: 875
OD: OverDrivePct: 0
SMU is initialized successfully!
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 408289520
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 86 data: 1482031344
[drm] Display Core initialized with v3.2.69!
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 1
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 0
[BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 54000
100 rate = 14
101 lane = 4 framing = 1
107 spread = 10
0x102 pattern = 1
0x102 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 11
0x207 Lane23AdjustRequest = 11
0x103 VS set = 1 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x103 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 11
0x203 Lane23Status = 11
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x102 pattern = 3
0x102 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 400
0x202 Lane01Status = 77
0x203 Lane23Status = 77
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
102 pattern = 0
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] Driver supports precise vblank timestamp query.
[drm] kiq ring mec 2 pipe 1 q 0
[drm] VCN decode and encode initialized successfully(under DPG Mode).
[drm] JPEG decode initialized successfully.
amdgpufb0 at amdgpu0
amdgpu0: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
amdgpu0: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
amdgpu0: ring comp_1.0.0 uses VM inv eng 4 on hub 0
amdgpu0: ring comp_1.1.0 uses VM inv eng 5 on hub 0
amdgpu0: ring comp_1.2.0 uses VM inv eng 6 on hub 0
amdgpu0: ring comp_1.3.0 uses VM inv eng 7 on hub 0
amdgpu0: ring comp_1.0.1 uses VM inv eng 8 on hub 0
amdgpu0: ring comp_1.1.1 uses VM inv eng 9 on hub 0
amdgpu0: ring comp_1.2.1 uses VM inv eng 10 on hub 0
amdgpu0: ring comp_1.3.1 uses VM inv eng 11 on hub 0
amdgpu0: ring kiq_2.1.0 uses VM inv eng 12 on hub 0
amdgpu0: ring sdma0 uses VM inv eng 13 on hub 0
amdgpu0: ring sdma1 uses VM inv eng 14 on hub 0
amdgpu0: ring vcn_dec uses VM inv eng 0 on hub 1
amdgpu0: ring vcn_enc0 uses VM inv eng 1 on hub 1
amdgpu0: ring vcn_enc1 uses VM inv eng 4 on hub 1
amdgpu0: ring jpeg_dec uses VM inv eng 5 on hub 1
[drm] Initialized amdgpu 3.36.0 20150101 for amdgpu0 on minor 0
amdgpufb0: framebuffer at 0xd04c9000, size 2560×1440, depth 32, stride 10240
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:2560 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:2560 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:1280 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:1280 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:2560 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML: VStartup: 60
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:0 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[SCALER]:resource_build_scaling_params: Viewport:
height:1440 width:1280 x:1280 y:0
dst_rect:
height:1440 width:2560 x:0 y:0
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]: dispclk_mhz (calculated) = f[DML]: dppclk_mhz0 = f[DML]: dcfclk_mhz = f[DML]: return_bw_to_dcn = f[DML]: return_bus_bw = f[DML]: read_bw[0] = fBps[DML]: urgent_extra_latency = fus[DML]: wm_urgent = fus[DML]: wm_wb_urgent = fus[DML]: wm_pstate_change = fus[DML]: calculating wb pstate watermark[DML]: total wb outputs 0[DML]: socclk frequency f Mhz[DML]: wm_wb_pstate fus[DML]: dcfclk_deepsleep_per_plane[0] = fMHz[DML]: dcfclk_deepsleep_mhz = fMHz[DML]: wm_cstate_exit = fus[DML]: wm_cstate_enter_exit = fus[DML]:DML: VStartup: 13
[DML]:DML: TCalc: f
[DML]:DML: TWait: f
[DML]:DML: XFCRemoteSurfaceFlipDelay: f
[DML]:DML: LineTime: f
[DML]:DML: Tsetup: f
[DML]:DML: Tdm: f
[DML]:DML: DSTYAfterScaler: f
[DML]:DML: DSTXAfterScaler: f
[DML]:DML: HTotal: 2817
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[0] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: t_mclk_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_urg_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_sr_wm_us = f
[DML]:DML_RQ_DLG_CALC: t_extra_us = f
[DML]:DML_RQ_DLG_CALC: t_srx_delay_us = f
[DML]:DML_RQ_DLG_CALC: deepsleep_dcfclk_mhz = f
[DML]:DML_RQ_DLG_CALC: total_flip_bw = f
[DML]:DML_RQ_DLG_CALC: total_flip_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] start

[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: cstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pstate_en = 1
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dppclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dispclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pclk_freq_in_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: interlaced = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dcfclk_mhz = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: min_dst_y_ttu_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: t_calc_us = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: disp_dlg_regs->min_dst_y_next_start = 0x1769
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: ref_freq_to_pix_freq = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: htotal = 2817
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: pixel_rate_delay_subtotal = 310
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_x_after_scaler = 1590
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_after_scaler = 0
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_prefetch (after rnd) = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_vm_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: dst_y_per_row_vblank = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: lsw = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_l= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: vratio_pre_c= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 1
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: full_recout_width = 2560
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: hscale_pixel_rate_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_line_delivery_l = f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: get_refcyc_per_delivery: refclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: pclk_freq_in_mhz = f
[DML]:DML_DLG: get_refcyc_per_delivery: recout_width = 2560
[DML]:DML_DLG: get_refcyc_per_delivery: vratio = f
[DML]:DML_DLG: get_refcyc_per_delivery: req_per_swath_ub = 21
[DML]:DML_DLG: get_refcyc_per_delivery: refcyc_per_delivery= f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_pre_l = f
[DML]:DML_DLG: dml20v2_rq_dlg_get_dlg_params: refcyc_per_req_delivery_l = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_width = 64
[DML]:DML_DLG: calculate_ttu_cursor: cur_width_ub = f
[DML]:DML_DLG: calculate_ttu_cursor: cur_req_per_width = f
[DML]:DML_DLG: calculate_ttu_cursor: hactive_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_pre_cur = f
[DML]:DML_DLG: calculate_ttu_cursor: refcyc_per_req_delivery_cur = f
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_TTU_REGS_ST
[DML]:DML_RQ_DLG_CALC: qos_level_low_wm = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_high_wm = 0x328
[DML]:DML_RQ_DLG_CALC: min_ttu_vblank = 0x388
[DML]:DML_RQ_DLG_CALC: qos_level_flip = 0xe
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_l = 0x22fb
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur0 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: refcyc_per_req_delivery_pre_cur1 = 0x125d
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_l = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_l = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_c = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_c = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur0 = 0x8
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur0 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_level_fixed_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: qos_ramp_disable_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DLG_REGS_ST
[DML]:DML_RQ_DLG_CALC: refcyc_h_blank_end = 0x11
[DML]:DML_RQ_DLG_CALC: dlg_vblank_end = 0x36
[DML]:DML_RQ_DLG_CALC: min_dst_y_next_start = 0x1769
[DML]:DML_RQ_DLG_CALC: refcyc_per_htotal = 0xca17
[DML]:DML_RQ_DLG_CALC: refcyc_x_after_scaler = 0x72
[DML]:DML_RQ_DLG_CALC: dst_y_after_scaler = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_prefetch = 0xc
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_vblank = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_vblank = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_per_vm_flip = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_row_flip = 0x0
[DML]:DML_RQ_DLG_CALC: ref_freq_to_pix_freq = 0x92ec
[DML]:DML_RQ_DLG_CALC: vratio_prefetch = 0x80000
[DML]:DML_RQ_DLG_CALC: vratio_prefetch_c = 0x80000
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_l = 0x4b
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_vblank_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_c = 0x97
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_l = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_flip_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_l = 0x200
[DML]:DML_RQ_DLG_CALC: dst_y_per_pte_row_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_l = 0x3285
[DML]:DML_RQ_DLG_CALC: refcyc_per_pte_group_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_l = 0x20
[DML]:DML_RQ_DLG_CALC: dst_y_per_meta_row_nom_c = 0x20
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_l = 0x650
[DML]:DML_RQ_DLG_CALC: refcyc_per_meta_chunk_nom_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_pre_c = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_l = 0xb7
[DML]:DML_RQ_DLG_CALC: refcyc_per_line_delivery_c = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur0 = 0x3
[DML]:DML_RQ_DLG_CALC: dst_y_offset_cur1 = 0x0
[DML]:DML_RQ_DLG_CALC: chunk_hdl_adjust_cur1 = 0x3
[DML]:DML_RQ_DLG_CALC: vready_after_vcount0 = 0x1
[DML]:DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x7fff
[DML]:DML_RQ_DLG_CALC: xfc_reg_transfer_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_precharge_delay = 0x0
[DML]:DML_RQ_DLG_CALC: xfc_reg_remote_surface_flip_latency = 0x0
[DML]:DML_RQ_DLG_CALC: refcyc_per_vm_dmdata = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_DLG: Calculation for pipe[1] end
[DML]:DML_DLG: get_meta_and_pte_attr: surf_linear = 1
[DML]:DML_DLG: get_meta_and_pte_attr: surf_vert = 0
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_width = 64
[DML]:DML_DLG: get_meta_and_pte_attr: blk256_height = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_height = 64
[DML]:DML_DLG: get_meta_and_pte_attr: meta_blk_width = 4096
[DML]:DML_DLG: get_meta_and_pte_attr: meta_surface_bytes = 0
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_req_per_frame_ub = 1
[DML]:DML_DLG: get_meta_and_pte_attr: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_DLG: handle_det_buf_split: req128_l = 0
[DML]:DML_DLG: handle_det_buf_split: req128_c = 0
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_l = 5376
[DML]:DML_DLG: handle_det_buf_split: full_swath_bytes_packed_c = 0
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_PARAM_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: ===
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 0
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 1344
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 21
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 64
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 41
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 2
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 128
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 2624
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 1
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 4
[DML]:DML_RQ_DLG_CALC: meta_row_height = 8
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 256
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_DLG_PARAM_ST
[DML]:DML_RQ_DLG_CALC: swath_width_ub = 0
[DML]:DML_RQ_DLG_CALC: swath_height = 1
[DML]:DML_RQ_DLG_CALC: req_per_swath_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_pte_bytes_per_frame_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_groups_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: dpte_row_height = 0
[DML]:DML_RQ_DLG_CALC: dpte_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_chunks_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_req_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: meta_row_height = 0
[DML]:DML_RQ_DLG_CALC: meta_bytes_per_row_ub = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 5376
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 10752
[DML]:DML_RQ_DLG_CALC: blk256_width = 64
[DML]:DML_RQ_DLG_CALC: blk256_height = 1
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_MISC_PARAM_ST
[DML]:DML_RQ_DLG_CALC: full_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: stored_swath_bytes = 0
[DML]:DML_RQ_DLG_CALC: blk256_width = 0
[DML]:DML_RQ_DLG_CALC: blk256_height = 0
[DML]:DML_RQ_DLG_CALC: req_width = 0
[DML]:DML_RQ_DLG_CALC: req_height = 0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: *
[DML]:DML_DLG: extract_rq_sizing_regs: rq_sizing param
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_SIZING_PARAM_ST
[DML]:DML_RQ_DLG_CALC: chunk_bytes = 8192
[DML]:DML_RQ_DLG_CALC: min_chunk_bytes = 1024
[DML]:DML_RQ_DLG_CALC: meta_chunk_bytes = 2048
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_bytes = 256
[DML]:DML_RQ_DLG_CALC: mpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: dpte_group_bytes = 2048
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x1
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x3
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x5
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x4
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC:
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: DISPLAY_DATA_RQ_REGS_ST
[DML]:DML_RQ_DLG_CALC: chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: min_meta_chunk_size = 0x0
[DML]:DML_RQ_DLG_CALC: dpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: mpte_group_size = 0x0
[DML]:DML_RQ_DLG_CALC: swath_height = 0x0
[DML]:DML_RQ_DLG_CALC: pte_row_height_linear = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[DML]:DML_RQ_DLG_CALC: drq_expansion_mode = 0x2
[DML]:DML_RQ_DLG_CALC: prq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: mrq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: crq_expansion_mode = 0x1
[DML]:DML_RQ_DLG_CALC: plane1_base_address = 0x0
[DML]:DML_RQ_DLG_CALC: =====================================
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 20, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 21, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 22, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 23, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 24, colorDepth = 0
[BIOS]:set_pixel_clock_v7:program display clock = 0, tg = 255, pll = 25, colorDepth = 0
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =10646
HW register value = 0x214
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =10239
HW register value = 0x1ff
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =17546
HW register value = 0x36d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =15475
HW register value = 0x305
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =17139
HW register value = 0x358
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =15068
HW register value = 0x2f1
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =40646
HW register value = 0x7f0

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =40239
HW register value = 0x7db

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =38989
HW register value = 0x79d

[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 1
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 37 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 37 data: 131073
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 40 data: 117901057
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 41 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 42 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 43 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 44 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 45 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 46 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 47 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 49 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 50 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 51 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 53 data: 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 56 data: 1
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 56 data: 1
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 55 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 58 data: 913509922
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 59 data: 13
[HW_AUDIO]:
AUDIO:az_configure: index: 2 data, 0xd, displayName OMEN 27i IPS:
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 60 data: 1431864734
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 61 data: 228103241
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 62 data: 1313164623
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 63 data: 1765224992
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 64 data: 1397770528
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 65 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 66 data: 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 17
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 16
[BIOS]:set_pixel_clock_v7:program display clock = 6969600, tg = 0, pll = 11, colorDepth = 0
[BIOS]:transmitter_control_v1_6:ps.param.symclk_10khz = 54000
100 rate = 14
101 lane = 4 framing = 1
107 spread = 10
0x102 pattern = 1
0x102 VS set = 0 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 11
0x207 Lane23AdjustRequest = 11
0x103 VS set = 1 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 0
0x203 Lane23Status = 0
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x103 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 100
0x202 Lane01Status = 11
0x203 Lane23Status = 11
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
0x102 pattern = 3
0x102 VS set = 2 PE set = 0 max VS Reached = 0 max PE Reached = 0
wait = 400
0x202 Lane01Status = 77
0x203 Lane23Status = 77
0x206 Lane01AdjustRequest = 22
0x207 Lane23AdjustRequest = 22
102 pattern = 0
[HW_AUDIO]:AUDIO:read_indirect_azalia_reg: index: 84 data: 0
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 2147483649
[HW_AUDIO]:AUDIO:write_indirect_azalia_reg: index: 84 data: 2147483648
[HW_AUDIO]:
========= AUDIO:dce_aud_az_enable: index: 2 data: 0x80000000
[HDCP_TOP]:
[HDCP_TOP]:[Link 0] mod_hdcp_add_display display 1[BANDWIDTH_CALCS]:URGENCY_WATERMARK_A calculated =10646
HW register value = 0x214
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_A calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_B calculated =10239
HW register value = 0x1ff
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_B calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_C calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_C calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:URGENCY_WATERMARK_D calculated =8989
HW register value = 0x1c1
[BANDWIDTH_CALCS]:PTE_META_URGENCY_WATERMARK_D calculated =4000
HW register value = 0xc8
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_A calculated =17546
HW register value = 0x36d
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_A calculated =15475
HW register value = 0x305
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_B calculated =17139
HW register value = 0x358
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_B calculated =15068
HW register value = 0x2f1
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_C calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_C calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:SR_ENTER_EXIT_WATERMARK_D calculated =15889
HW register value = 0x31a
[BANDWIDTH_CALCS]:SR_EXIT_WATERMARK_D calculated =13819
HW register value = 0x2b2
[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =40646
HW register value = 0x7f0

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =40239
HW register value = 0x7db

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_A calculated =40646
HW register value = 0x7f0

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_B calculated =40239
HW register value = 0x7db

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_C calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:DRAM_CLK_CHANGE_WATERMARK_D calculated =38989
HW register value = 0x79d

[BANDWIDTH_CALCS]:Current: dispclk_khz:707449 max_dppclk_khz:350222 dcfclk_khz:506000
dcfclk_deep_sleep_khz:43560 fclk_khz:506000 socclk_khz:506000
[BANDWIDTH_CALCS]:Calculated: dispclk_khz:707449 max_dppclk_khz:350222 dcfclk_khz:506000
dcfclk_deep_sleep_khz:43560 fclk_khz:506000 socclk_khz:506000
wsdisplay0 at amdgpufb0 kbdmux 1: console (default, vt100 emulation), using wskbd0
wsmux1: connecting to wsdisplay0
wskbd1: connecting to wsdisplay0
{drm:netbsd:gfx_v10_0_ring_test_ib+0x179} ERROR amdgpu: IB test timed out.
amdgpu0 {drm:netbsd:amdgpu_ib_ring_tests+0xdf} ERROR IB test failed on kiq_2.1.0 (-60).
{drm:netbsd:linux_workqueue_thread+0x15e} ERROR ib ring test failed (-60).
aq0: link is UP: speed=10000
[HDCP_TOP]:[Link 0] add display 1wsdisplay0: screen 1 added (default, vt100 emulation)
wsdisplay0: screen 2 added (default, vt100 emulation)
wsdisplay0: screen 3 added (default, vt100 emulation)
wsdisplay0: screen 4 added (default, vt100 emulation)

NetBSD 10 RC6

NetBSD 10 is really close to final release now, the 6th release candidate was prepared on 12th of March, 2024. Last few RC releases were mainly focusing on security and minor fixes. Currently release is scheduled by the end of March, however the date is not set in stone and one or more release candidates can be prepared.

The formal release announcement is available here and should be updated for the any interim RC releases, including the final one in the same link. It took more than a year after netbsd-10 was branched to reach first RC release and few months passed after that. Not everything is perfect, a new DRM/KMS subsystem version supports more hardware, but also may lead to failures where it worked before. Supported graphics card may have different issues as well. Hopefully, they will be addressed in the future releases. However, the release brings strong performance improvements, plenty of new hardware support and device drivers, improvements to modern and legacy/vintage systems, new features and enhancements, multiple updates to third-party software and much more. Please test it! Download links for multiple platforms are available in the official blog post, more images can be explored from the CDN . And please report bugs here.

Booting NetBSD on HP 620LX

Few weeks ago I got an opportunity to buy HP 620LX handheld PC. It is a small device based on Hitachi SH7709 SH-3 ~75MHz SoC with 16MB RAM, one CompactFlash slot and one CardBus (PCMCIA) slot. It also has an option to connect serial cable (cable comes with the device). The default operating system is Windows CE 2.0 (or 2.11 if you are lucky to find the ROM upgrade).

System was untested and didn’t have original power adapter, however was packaged in original box with most accessories available. Fortunately, the system booted successfully using 12V 1A adapter (the original adapter provides 2A if I am not mistaken), giving me an opportunity to test NetBSD on it. HP 620LX is supported by hpcsh port, which aims to run on various handheld devices based on SH-3/4 SoCs.

Installation process is not completely trivial on this type of devices. One important point is that booting NetBSD will completely reset Windows CE device, loosing all configuration and data, thus backup is required, if it contains something important to the user (not in my case). There’s no sysinst(8) support, CF memory card should be prepared in advance on another NetBSD system. The instructions are available here, even more detailed instructions can be found here (thanks @uwe for pointing this document in the mailing list). To make the long story short: two partitions should be prepared: one DOS partition of the “small” size (20-30MB), and at least one FFS partition for NetBSD root partition. The DOS partition needs to include kernel file and a boot loader application. Distribution sets should be extracted to the NetBSD partition(s) (at least base, etc IMHO), and initial configuration can be done for /etc/rc.conf, /etc/fstab, etc.

Once everything is ready, hpcboot.exe needs to be executed from Windows CE. Choosing the right bootloader executable appeared to be the first challenge though. Installation directory in the port’s distribution contains sh3-hpcboot.exe and sh4-hpcboot.exe with seemingly the obvious choice for SH-3 based device. The caveat is that the binary is build for Windows CE 2.11 and above, and it fails to run on Windows CE 2.0. My initial fear was that I would need to build one myself with the right tools. Fortunately, I found one in the NetBSD code instead. It is uuencoded, thus should be decoded first by running command uudecode -o hpcboot.exe hpcboot200.exe.uue. The bootloader program allows to choose the device and several boot flags, and after few seconds NetBSD boot messages appear on the screen. On initial boot I faced the second issue, related to disk labels. The main reason was that my FFS partition was not labeled as wd0a. It appeared to be an easy fix sudo disklabel -e /dev/rsd3 (rsd3 may differ on your device) and just edit and save label from f->a (in my case) in the opened editor. Soon after I had a properly booting system and could successfully login to the system. Here the final configuration can be performed, like creation of users, setting the passwords, etc.

What’s next? First of all, I plan to add hpc200.exe to distribution files. After, I would like to enable some of my pcmcia devices (wifi card and SATA card), test network, test serial, and just to keep port a little bit more alive! Time will tell.

Enjoy dmesg below for now:

NetBSD 10.99.9 on HP 620LX

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013,
2014, 2015, 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.

NetBSD 10.99.9 (GENERIC) #0: Wed Oct 4 07:51:36 UTC 2023
mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/hpcsh/compile/GENERIC
HP 620LX
total memory = 16384 KB
avail memory = 12896 KB
timecounter: Timecounters tick every 15.625 msec
mainbus0 (root)
cpu0 at mainbus0: SH3 73.728 MHz PCLOCK 18.432 MHz
cpu0: 16KB/16B 4-way set-associative I/D-unified cache.
cpu0: U0, P0, P3 write-back; P1 write-through
cpu0: 4-way set-associative 128 TLB entries
cpu0: VPN mode, multiple virtual storage mode
btnmgr0 at mainbus0
wskbd2 at btnmgr0 mux 1
shb0 at mainbus0
rtc0 at shb0
scif0 at shb0
adc0 at shb0
j6x0tp0 at adc0
wsmouse0 at j6x0tp0 mux 0
wskbd1 at j6x0tp0 mux 1
j6x0lcd0 at shb0: brightness 21, contrast 21
hd64461if0 at shb0
hd64461video0 at hd64461if0: frame buffer = 512 KB , console
hpcfb0 at hd64461video0: 640×240 pixels, 256 colors, 80×24 chars
wsdisplay0 at hpcfb0 kbdmux 1: console (std, vt100 emulation)
wsmux1: connecting to wsdisplay0
wskbd2: connecting to wsdisplay0
wskbd1: connecting to wsdisplay0
hpcfb: 640×240 pixels, 256 colors, 80×24 chars
hpcfb: 640×240 pixels, 256 colors, 80×24 chars
hpcfb: 640×240 pixels, 256 colors, 80×24 chars
wsdisplay0: screen 1-3 added (std, vt100 emulation)
hd64461pcmcia0 at hd64461if0
com0 at hd64461if0autoconfiguration error: : device problem. don’t attach.
pfckbd0 at mainbus0
hpckbd0 at pfckbd0
wskbd0 at hpckbd0: console keyboard, using wsdisplay0
hpcapm0 at mainbus0: pseudo power management module
apmdev0 at hpcapm0: Power Management spec V1.2
timecounter: Timecounter “tmu_pclock_4” frequency 4608075 Hz quality 0
timecounter: Timecounter “clockinterrupt” frequency 64 Hz quality 0
pcmcia0 at hd64461pcmcia0
pcmcia1 at hd64461pcmcia0
wdc0 at pcmcia1 function 0:
wdc0: memory mapped mode
WARNING: system needs entropy for security; see entropy(7)
atabus0 at wdc0 channel 0
wd0 at atabus0 drive 0
wd0:
wd0: drive supports 1-sector PIO transfers, LBA addressing
wd0: 488 MB, 993 cyl, 16 head, 63 sec, 512 bytes/sect x 1000944 sectors
wd0: 32-bit data port
swwdog0: software watchdog initialized
WARNING: 1 error while detecting hardware; check system log.
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
kern.module.path=/stand/hpcsh/10.99.9/modules
entropy: best effort

Hunting for vte(4) bug on VortexDX86 SoC based system

The NetBSD 9.3 and OpenBSD 7.2 (and upcoming FreeBSD 14.0) releases include one small fix to the establishment of RDC R6040 (vte(4)) Ethernet controller’s link on DM&P Vortex86DX3 dual-core SoC. More than that, the similar patch was applied on Linux kernel as well, making it my first contribution to all major BSDs and Linux. It is only few lines in the code, but it was a long journey to identify it. Thus, I decided to write a small article with the hope to encourage people to work on such issues.

Back in 2018, I bought a small DM&P Vortex86DX3 SoC based system, called eBox 3352DX3-AP. It is USB powered fanless system, which includes few I/O ports: 3xUSB 2.0 ports, 1xVGA (Vortex86VGA), 1xSD Card slot and one 100Mbit Ethernet RJ-45 port (RDC R6040 MAC). AP abbreviation means auto-power, which indicates that it doesn’t have physical power button and starts automatically as soon as power cable is connected to it. NetBSD was, of course, the first OS I’ve tried to boot on it. Unfortunately, it wasn’t seamless experience, the two major issues were clear on the initial attempts:

  • ACPI/SMP needed to be disabled, otherwise USB (and later identified that all other devices (audio/network), using legacy PCI INTx interrupts) will fail to work. This issue is still unresolved, and it is NetBSD/OpenBSD specific (any help appreciated!). FreeBSD/Linux does seem to be capable in handling those interrupts without any issues.
  • R6040 Ethernet controller failed to work, doesn’t matter if ACPI was enabled or disabled. At the point of discovery I thought that it was BSD specific (affected all of them the same way), but later on it appeared to be the issue in Linux as well, even though 4.x and early 5.x kernel versions worked with the controller due to the way Linux was establishing the connection.

I took a priority on investigating network controller issue with the hope, that it would be easier to solve, and additionally would allow to use SSH to connect to the device on ACPI boot (I didn’t know yet that level interrupts causing the failure, on network controller won’t work without fixing that). More than that, I really hoped to resolve it pretty fast, compared to quite troublesome navigation between USB and/or ACPI/APIC code. Unfortunately, I was quite wrong with this assumption. It took me around 3 years to identify the cause and apply the final patch! Nevertheless, I had a working device much sooner than that, but let’s start story from the beginning .

Initial investigation

The first step is always to check dmesg(8) messages of the system and check ifconfig vte0 command output. On my PR report I stated that PHY OUI was not the same as the driver expected (0xfcff2f vs 0x00d02d) and it had a “new” model (0x0005 instead of 0x0003). Because of that general phy driver (ukphy(4)) was attached instead of rdcphy(4) driver. MAC controller (vte) was recognized correctly and attached as expected though.

vte0 at pci0 dev 8 function 0: vendor 17f3 product 6040 (rev. 0x00)
vte0: Ethernet address xx:xx:xx:xx:xx:xx
vte0: interrupting at irq 5
ukphy0 at vte0 phy 1: OUI 0xfcff2f, model 0x0005, rev. 0
ukphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto

As the first step, I started by adding a “new” oui and model to miidevs file, and included it in rdcphy.c phys list, so it can be recognized and used instead of generic one. Even though rdcphy attached successfully after the changes, the link state remained unset. Disappointed, I took a more careful look into the phy driver code. Main focus was on the MII_MEDIACHG case, and especially rdcphy_status() method. I didn’t find anything wrong with MII_MEDIACHG, but status method had at least 4 conditional statements before it sets media link! That was a really good spot to go deeper. Especially on two specific conditional statements.

Running ifconfig vte0 revealed that link wasn’t established: media: Ethernet autoselect (none). Manual attempts to set the link and its speed were unsuccessful too. This behavior was the same in FreeBSD and OpenBSD. Linux was working though (used SparkyLinux distribution with some 4.x kernel). The connection wasn’t always stable, but it worked. It also gave me a additional false hope to resolve this soon, since I assumed it may be enough to compare drivers and see what was different between them.


	PHY_READ(sc, MII_BMSR, &bmsr);
	PHY_READ(sc, MII_BMSR, &bmsr);
	PHY_READ(sc, MII_RDCPHY_STATUS, &physts);

	if ((physts & STATUS_LINK_UP) != 0)
		mii->mii_media_status |= IFM_ACTIVE;

	PHY_READ(sc, MII_BMCR, &bmcr);
	if ((bmcr & BMCR_ISO) != 0) {
		mii->mii_media_active |= IFM_NONE;
		mii->mii_media_status = 0;
		return;
	}

	if ((bmcr & BMCR_LOOP) != 0)
		mii->mii_media_active |= IFM_LOOP;

	if ((bmcr & BMCR_AUTOEN) != 0) {
		if ((bmsr & BMSR_ACOMP) == 0) {
			/* Erg, still trying, I guess... */
			mii->mii_media_active |= IFM_NONE;
			return;
		}
	}

From the rdcphy(4) code above we can see that bmsr (Basic Mode Status Register) register is being read twice, and may be used later to check if auto-negotiation is still in progress. However, the first check compares MII_RDCPHY_STATUS register value against STATUS_LINK_UP mask to set device active. Finally, bmcr (Basic Mode Control Register) register value is checked against BMCR_ISO mask to decide if driver can proceed or link status can’t be identified. This condition picked my eyes, since ifconfig was showing that media link status is “none”. I printed values of all of these three registers and it appeared that BMCR and MII_RDCPHY_STATUS always reports 0xffff. BMSR value was correct on the other hand. Thus, first patch was to ignore all these if conditions and set media link to IFM_100_TX “by force” in the code. Quite surprisingly, it worked! Network controller established the link and successfully auto-negotiated IP address. Obviously it was not a solution to commit, but it worked as initial workaround and could be applied locally.

Comparison with Linux driver

At this point I started to compare the driver to Linux kernel counterpart, including its various older iterations. Unfortunately, the code functionally was very similar, except few small differences. Of course, those can be vital sometimes, but over the time I tried to match both drivers as close as possible without any positive results. The biggest hopes were associated with this part:

	/* If PHY status change register is still set to zero it means the
	 * bootloader didn't initialize it, so we set it to:
	 * - enable phy status change
	 * - enable all phy addresses
	 * - set to lowest timer divider */
	if (ioread16(ioaddr + PHY_CC) == 0)
		iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
				7 << TMRDIV_SHIFT, ioaddr + PHY_CC);

The comment above states, if PHY_CC register has value 0, the PHY status change register wasn’t initialized yet by the boot loader. Writing certain value to it would enable phy status change, would enable all PHY addresses and would set to the lowest timer divider. I was so convinced that it was a missing link, that disappointment was really great, once it appeared not to be the case. No matter where I applied this code, it had no effect on resolving the issue. Soon after I started to print all PHY register values, which indicated that every second register address returns 0xffff. And it seems that those were mainly “write” registers, read-only ones were successfully returning values. I was stuck with no solid ideas how to move forward after that.

Next lead – controller reset function

I didn’t give up completely though. I was trying to change or comment various places in the code, especially in device initialization code (vte_init, vte_attach). While doing so, I was still printing registry values and comparing dmesg. During some of those experiments, I noticed that commenting out vte_reset() call suddenly changes the situation, network controller starts to work, rdcphy OUI becomes an expected value, registered for RDC devices (0x00d02d instead of 0xfcff2f). And the most importantly, all PHY registers started to print “correct” values, by which I mean there were not 0xffff anymore! Additional tests showed that calling this function once is enough to make controller to stop working (even more specifically any of CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET) or CSR_WRITE_2(sc, VTE_MACSM, 0x0002); and CSR_WRITE_2(sc, VTE_MACSM, 0); calls would result to reproducible issue). Surprisingly, Linux MAC reset code was doing exactly the same thing(!), leaving me confused on why the code works on this system. It was pretty important breakthrough, which not only allowed to simplify temporary patch to commenting out MAC reset code, but it finally enabled me to focus on much more narrow space. What is more, I could compare register values before and after reset. Initially, I believed that, it might be an issue of the 0x0005 model, but this theory was debunked soon by checking submitted dmesg outputs in dmesgd.nycbug.org (it is really helpful database of dmesg outputs(!)). I quickly found dmesg outputs of the systems with the different DM&P Vortex86 SoC models (not DX3) printing correct OUI value for the same 0x0005 model, meaning vte_reset() wasn’t affecting them in the same way as my system.

At this point, I really wanted to check directly how Linux actually behaves, but I failed to build a boot-able kernel (much later I found out it’s because of too big initrd, but I will come back on that later). Additionally, there was no way to print phy OUI value, it is not available in dmesg, and all mii tools failed to print it. Instead, I managed to acquire a Vortex86DX2 SoC based system and started comparing register values before and after reset between two systems. Even though this comparison was indicating the issue, I failed to recognize it at that time. I saw few registers being different between two before reset and becoming the same after, however I just tried to set DX2 values before reset, which didn’t solve the issue. For quite a long time I was stuck again. I was endlessly reading Linux code (including older version of the driver), trying random patches on NetBSD driver, nevertheless failing to find any possible lead.

Vortex86EX2 and bootable custom Linux kernel

At some point I decided to buy one more Vortex86 based system, this time based on the newest Vortex86EX2 SoC. I didn’t buy it to investigation the issue specifically (had an application for it in my house network), but it gave me an opportunity to compare registry values between three systems now. EX2 was working out of the box, despite having even newer 0x0006 model PHY. The registry values appeared closer to DX2 system than DX3. I contacted ICOP support at that point (with whom I had a pleasant communication regarding other issues in the past), leading to the communication between different people, sister companies and even the original seller of DX3 system. Unfortunately, the final response was “we don’t know, Linux works, must be something wrong with BSD drivers”. It encouraged me to take one more attempt to build custom Linux kernel. This was the point when I realized that system fails to boot because of much bigger initrd file than the original was (thus it was exceeding the size of available RAM in the system). It appeared that I need to strip debug symbols by adding INSTALL_MOD_STRIP=1 property in make modules_install command. And the custom build Linux kernel booted successfully! I started to print registry values around MAC reset calls and, to my big surprise Linux had exactly the same issue on printing 0xffff value for every second register. It was the important turning point, indicating that Linux is equally affected and no magic happens. It took some time to understand by reading Linux code why it worked at all. Discussions with my colleague helped me to realize that I am reading the newest code only, while I should probably check the code of the kernel used by my current distribution. It appeared that previous Linux kernel versions used only BMSR register value to establish link before this commit, and this specific register still works well after reset. However, starting 5.3 kernel version BMCR register value was taken into account as well, making code closer to BSDs and PHY was failing to link up in the same way after that change. Just to be sure, I tested edge Sparky Linux distribution version, which used the newer kernel and confirmed that I couldn’t establish a link with R6040 Ethernet controller anymore without removing reset calls. At this point I almost completely gave up and I even decided to close my bug report, deemed my system to be likely broken.

Final issue identification and fix

Despite the decision to close my the bug report and I didn’t completely gave up on the debugging the issue. I was still pretty sure that it is something with registers and I decided yet again to look at the differences between my DX3 and DX2/EX2 systems. I re-identified two registers, whose would reset to different value and at least one of them would reset to the value original DX2/EX2 value before reset. DX2/EX2 register value wouldn’t change on the hand after reset. One of those registers was MDC (Management Data Input/Output Interface Clock) speed control register (defined as VTE_MDCSC in NetBSD). As previously, I attempted to set the DX2 value before the reset and nothing would change, or so it seemed. However, this time I decided to add more logging and print all register values not only before and after the reset, but before and after setting affected register value. It was this decision which allowed me to notice that registers start to go “crazy” not after reset action anymore, but after setting this register’s value to one after reset! After that, the fix was on the horizon, I just needed to set original register value before reset back after the MAC reset. I researched more on what this register do, and once I found out that it drives the clock by the MAC device to PHY, everything made sense to me. The default register value have been already defined in the NetBSD too (#define MDCSC_DEFAULT 0x0030). Thus the final fix had only few additional lines of code in MAC reset function:

static void
vte_reset(struct vte_softc *sc)
{
	uint16_t mcr;
	uint16_t mcr, mdcsc;
	int i;

	mdcsc = CSR_READ_2(sc, VTE_MDCSC);
	mcr = CSR_READ_2(sc, VTE_MCR1);
	CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
	for (i = VTE_RESET_TIMEOUT; i > 0; i--) {
@@ -1231,6 +1232,14 @@ vte_reset(struct vte_softc *sc)
	CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
	CSR_WRITE_2(sc, VTE_MACSM, 0);
	DELAY(5000);

	/*
	 * On some SoCs (like Vortex86DX3) MDC speed control register value
	 * needs to be restored to original value instead of default one,
	 * otherwise some PHY registers may fail to be read.
	 */
	if (mdcsc != MDCSC_DEFAULT)
		CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
}

It reads VTE_MDCSC value before reset and stores it to mdcsc variable. After the MAC reset, mdcsc value is compared to the default register value (0x0030), and being set to the original, if it is not equal to default. If it is the same as default, there is no need to set the same value again.

The bug report was reported on 3rd of August, 2018, the fix was committed on 30th of August, 2021. It took quite a lots of time and effort to discover, but it was really rewarding and educational, especially when it was eventually applied to all the major BSDs and Linux kernel code.

Unfortunately, network controller still doesn’t work on ACPI/SMP mode on NetBSD/OpenBSD, because of level interrupts failure, which makes USB/audio to fail as well, and it is another issue I need to identify and fix.

NetBSD 10 (BETA) branch was finally created

It took long three years to create a NetBSD 10 branch, however it is finally available for testing. Tangible performance improvement can be expected with this upcoming release, as well as improved hardware support, reworked cryptography, WireGuard compatibility (wg(4)), automatic swap encryption, new disk encryption methods, updated GPU drivers (up to Linux 5.6 level, however work is not fully complete and issues are expected), and obviously tons of new and updated hardware support. New ARM platforms include Apple M1, Raspberry Pi4, Rockchip RK356X, NXP i.MX 8M, Amlogic G12, Oracle Cloud ARM instances and others. Some bootable ARM images are available here. New network drivers include but not limited to 2.5Gbit Realtek support rge(4) (no Intel yet), 10/25/40 Intel network adapters ixl(4), Intel Ethernet Adaptive Virtual Function driver iavf(4), others like mcx(4) were significantly updated. Retro platforms also received some love, including improved Dec Alpha and iMac G5 support. Besides the kernel updates, there are lots of new changes in the userland as well like aiomixer(1), blkdiscard(8) and fsck_udf(8). Download links for multiple platforms are available in the official blog post, more images can be explored in nycdn continuous builds. Please report bugs here.

NetBSD 10.0 BETA on Ryzen 5 3600

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017,
2018, 2019, 2020, 2021, 2022
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.

NetBSD 10.0_BETA (GENERIC_AMDGPU) #0: Fri Dec 23 23:31:34 EET 2022
andriusv@agraphic-pc:/home/andriusv/netbsd-src/sys/arch/amd64/compile/GENERIC_AMDGPU
total memory = 32712 MB
avail memory = 31623 MB
Prep module path=usbverbose len=82512 pa=1d3e000
pool redzone disabled for ‘buf2k’
pool redzone disabled for ‘buf4k’
pool redzone disabled for ‘buf32k’
pool redzone disabled for ‘buf64k’
pool redzone disabled for ‘sigacts’
pool redzone disabled for ‘mclpl’
pool redzone disabled for ‘dirhashblk’
pool redzone disabled for ‘dirhashblk’
timecounter: Timecounters tick every 10.000 msec
Kernelized RAIDframe activated
RTC BIOS diagnostic error 0xf
timecounter: Timecounter “i8254” frequency 1193182 Hz quality 100
efi: systbl at pa bdf61018
efi: systbl mapped at va ffffde085abec018
efi: signature 5453595320494249 revision 20046 crc32 206adc0f
efi: firmware revision 50011
efi: runtime services at pa 0xbdf61b98
efi: boot services at pa 0x0
efi: cfgtbl at pa bdf61c98
efi: cfgtbl mapped at va ffffde085abeec98
efi: 14 cfgtbl entries:
efi: 0xbca5b698 ee4e5898-3914-4259-9d6e-dc7bd79403cf
efi: 0xbe578c10 05ad34ba-6f02-4214-952e-4da0398e2bb9
efi: 0xbca30018 7739f24c-93d7-11d4-9a3a-0090273fc14d
efi: 0xbe579480 4c19049f-4137-4dd3-9c10-8b97a83ffdfa
efi: 0xbe57a988 49152e77-1ada-4764-b7a2-7afefed95e8b
efi: 0xbdf60518 00781ca1-5de3-405f-abb8-379c3c076984
efi: 0xbd485000 eb9d2d30-2d88-11d3-9a16-0090273fc14d ACPI 1.0
efi: 0xbd485014 8868e871-e4f1-11d3-bc22-0080c73c8881 ACPI 2.0
efi: 0xbd44f000 1e2ed096-30e2-4254-bd89-863bbef82325
efi: 0xbde06000 eb9d2d31-2d88-11d3-9a16-0090273fc14d SMBIOS
efi: 0xbde05000 f2fd1544-9794-4a2c-992e-e5bbcf20e394 SMBIOS3
efi: 0xbcd6ff18 4e28ca50-d582-44ac-a11f-e3d56526db34
efi: 0xb8e55018 dcfa911d-26eb-469f-a220-38b7dc461220
efi: 0xb9460e18 b122a263-3661-4f68-9929-78f8b0d62180
efi_runtime_init: map 2758 pages at 0 to 0xbd49c000 type 6 attrs 0x800000000000000f
efi_runtime_init: map 157 pages at 0 to 0xbdf62000 type 5 attrs 0x800000000000000f
efi_runtime_init: map 32768 pages at 0 to 0xf0000000 type 11 attrs 0x800000000000100d
efi_runtime_init: map 256 pages at 0 to 0xfd200000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 512 pages at 0 to 0xfd600000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 16 pages at 0 to 0xfea00000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 130 pages at 0 to 0xfeb80000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 1 pages at 0 to 0xfec10000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 1 pages at 0 to 0xfec30000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 1 pages at 0 to 0xfed00000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 5 pages at 0 to 0xfed40000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 16 pages at 0 to 0xfed80000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 14 pages at 0 to 0xfedc2000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 2 pages at 0 to 0xfedd4000 type 11 attrs 0x8000000000000001
efi_runtime_init: map 4096 pages at 0 to 0xff000000 type 11 attrs 0x8000000000000001
SMBIOS rev. 3.3.0 @ 0xe6c70
mainbus0 (root)
ACPI: RSDP 0x00000000BD485014 000024 (v02 ALASKA)
ACPI: XSDT 0x00000000BD484728 0000C4 (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: FACP 0x00000000BCDB9000 000114 (v06 ALASKA A M I 01072009 AMI 00010013)
ACPI: DSDT 0x00000000BCDB3000 0056FB (v02 ALASKA A M I 01072009 INTL 20120913)
ACPI: FACS 0x00000000BD47F000 000040
ACPI: BHMB 0x00000000BCDC0000 000474 (v01 ALASKA A M I 00000001 AMI 00000001)
ACPI: SSDT 0x00000000BCDBF000 00092A (v02 AMD AmdTable 00000002 MSFT 04000000)
ACPI: SSDT 0x00000000BCDBB000 003BDD (v01 AMD AMD AOD 00000001 INTL 20120913)
ACPI: SSDT 0x00000000BCDBA000 0000C8 (v02 ALASKA CPUSSDT 01072009 AMI 01072009)
ACPI: FIDT 0x00000000BCDB2000 00009C (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: MCFG 0x00000000BCDB1000 00003C (v01 ALASKA A M I 01072009 MSFT 00010013)
ACPI: HPET 0x00000000BCDB0000 000038 (v01 ALASKA A M I 01072009 AMI 00000005)
ACPI: IVRS 0x00000000BCDAF000 0000D0 (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: FPDT 0x00000000BCDAE000 000044 (v01 ALASKA A M I 01072009 AMI 01000013)
ACPI: BGRT 0x00000000BCDAD000 000038 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: TPM2 0x00000000BCDAC000 00004C (v04 ALASKA A M I 00000001 AMI 00000000)
ACPI: PCCT 0x00000000BCDAB000 00006E (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: SSDT 0x00000000BCDA7000 003047 (v02 AMD AmdTable 00000001 AMD 00000001)
ACPI: CRAT 0x00000000BCDA6000 000BD0 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: CDIT 0x00000000BCDA5000 000029 (v01 AMD AmdTable 00000001 AMD 00000001)
ACPI: SSDT 0x00000000BCDA1000 0037B0 (v01 AMD MYRTLE 00000001 INTL 20120913)
ACPI: SSDT 0x00000000BCDA0000 0000BF (v01 AMD AmdTable 00001000 INTL 20120913)
ACPI: WSMT 0x00000000BCD9F000 000028 (v01 ALASKA A M I 01072009 AMI 00010013)
ACPI: APIC 0x00000000BCD9E000 00015E (v03 ALASKA A M I 01072009 AMI 00010013)
ACPI: 7 ACPI AML tables successfully acquired and loaded
ioapic0 at mainbus0 apid 13: pa 0xfec00000, version 0x21, 24 pins
ioapic1 at mainbus0 apid 14: pa 0xfec01000, version 0x21, 32 pins
cpu0 at mainbus0 apid 0
cpu0: 16 page colors
cpu0: Use mfence to serialize rdtsc
cpu0: TSC freq from delay 3654164880 Hz
cpu0: [re]calibrating local timer
cpu0: apic clock running at 99 MHz
cpu0: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu0: node 0, package 0, core 0, smt 0
cpu1 at mainbus0 apid 2
cpu1: 2 page colors
cpu1: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu1: node 0, package 0, core 1, smt 0
cpu2 at mainbus0 apid 4
cpu2: 2 page colors
cpu2: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu2: node 0, package 0, core 2, smt 0
cpu3 at mainbus0 apid 8
cpu3: 2 page colors
cpu3: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu3: node 0, package 0, core 4, smt 0
cpu4 at mainbus0 apid 10
cpu4: 2 page colors
cpu4: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu4: node 0, package 0, core 5, smt 0
cpu5 at mainbus0 apid 12
cpu5: 2 page colors
cpu5: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu5: node 0, package 0, core 6, smt 0
cpu6 at mainbus0 apid 1
cpu6: 2 page colors
cpu6: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu6: node 0, package 0, core 0, smt 1
cpu7 at mainbus0 apid 3
cpu7: 2 page colors
cpu7: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu7: node 0, package 0, core 1, smt 1
cpu8 at mainbus0 apid 5
cpu8: 2 page colors
cpu8: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu8: node 0, package 0, core 2, smt 1
cpu9 at mainbus0 apid 9
cpu9: 2 page colors
cpu9: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu9: node 0, package 0, core 4, smt 1
cpu10 at mainbus0 apid 11
cpu10: 2 page colors
cpu10: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu10: node 0, package 0, core 5, smt 1
cpu11 at mainbus0 apid 13
cpu11: 2 page colors
cpu11: AMD Ryzen 5 3600 6-Core Processor , id 0x870f10
cpu11: node 0, package 0, core 6, smt 1
acpi0 at mainbus0: Intel ACPICA 20221020
acpi0: X/RSDT: OemId , AslId
allocated pic ioapic0 type level pin 9 level 6 to cpu0 slot 0 idt entry 96
acpi0: autoconfiguration error: invalid PCI address for D020
acpi0: autoconfiguration error: invalid PCI address for D025
acpi0: MCFG: segment 0, bus 0-127, address 0x00000000f0000000
MCFG: MEMMAP: 0x0000000000000000-0x000000000009ffff, size=0x00000000000a0000, type=1(Memory)
MCFG: MEMMAP: 0x00000000000a0000-0x00000000000fffff, size=0x0000000000060000, type=2(Reserved)
MCFG: MEMMAP: 0x0000000000100000-0x0000000009afefff, size=0x00000000099ff000, type=1(Memory)
MCFG: MEMMAP: 0x0000000009aff000-0x0000000009ffffff, size=0x0000000000501000, type=2(Reserved)
MCFG: MEMMAP: 0x000000000a000000-0x000000000a1fffff, size=0x0000000000200000, type=1(Memory)
MCFG: MEMMAP: 0x000000000a200000-0x000000000a210fff, size=0x0000000000011000, type=4(NVS)
MCFG: MEMMAP: 0x000000000a211000-0x000000000affffff, size=0x0000000000def000, type=1(Memory)
MCFG: MEMMAP: 0x000000000b000000-0x000000000b01ffff, size=0x0000000000020000, type=2(Reserved)
MCFG: MEMMAP: 0x000000000b020000-0x00000000bca5bfff, size=0x00000000b1a3c000, type=1(Memory)
MCFG: MEMMAP: 0x00000000bca5c000-0x00000000bcd95fff, size=0x000000000033a000, type=2(Reserved)
MCFG: MEMMAP: 0x00000000bcd96000-0x00000000bcdc0fff, size=0x000000000002b000, type=3(ACPI)
MCFG: MEMMAP: 0x00000000bcdc1000-0x00000000bd49bfff, size=0x00000000006db000, type=4(NVS)
MCFG: MEMMAP: 0x00000000bd49c000-0x00000000bdffefff, size=0x0000000000b63000, type=2(Reserved)
MCFG: MEMMAP: 0x00000000bdfff000-0x00000000beffffff, size=0x0000000001001000, type=1(Memory)
MCFG: MEMMAP: 0x00000000bf000000-0x00000000bfffffff, size=0x0000000001000000, type=2(Reserved)
MCFG: MEMMAP: 0x00000000f0000000-0x00000000f7ffffff, size=0x0000000008000000, type=2(Reserved)
acpi0: MCFG: segment 0, bus 0-127, address 0x00000000f0000000
acpi0: SCI interrupting at int 9
acpi0: fixed power button present
timecounter: Timecounter “ACPI-Safe” frequency 3579545 Hz quality 900
acpi0: ACPI-Safe 32-bit timer
hpet0 at acpi0: high precision event timer (mem 0xfed00000-0xfed00400)
timecounter: Timecounter “hpet0” frequency 14318180 Hz quality 2000
AMDN (PNP0C01) at acpi0 not configured
attimer1 at acpi0 (TMR, PNP0100): io 0x40-0x43 irq 0
pcppi1 at acpi0 (SPKR, PNP0800): io 0x61
spkr0 at pcppi1: PC Speaker
wsbell at spkr0 not configured
midi0 at pcppi1: PC speaker
sysbeep0 at pcppi1
pckbc1 at acpi0 (PS2K, PNP0303-0) (kbd port): io 0x60,0x64 irq 1
com0 at acpi0 (UAR1, PNP0501-0): io 0x3f8-0x3ff irq 4
com0: ns16550a, 16-byte FIFO
allocated pic ioapic0 type edge pin 4 level 8 to cpu0 slot 1 idt entry 129
acpibut0 at acpi0 (PWRB, PNP0C0C-170): ACPI Power Button
GPIO (AMDI0030) at acpi0 not configured
TPM (MSFT0101) at acpi0 not configured
PTIO (AMDIF030) at acpi0 not configured
acpitz0 at acpi0 (THRM)
acpitz0: polling interval 30.0 seconds
acpitz0: levels: critical 90.0 C, passive cooling
acpiwmi0 at acpi0 (AOD, PNP0C14-AOD): ACPI WMI Interface
acpiwmi0: {ABBC0F6A-8EA1-11D1-00A0-C90629100000} oid 4141 count 01 flags 02
acpiwmi0: {05901221-D566-11D1-B2F0-00A0C9062910} oid 4142 count 01 flags 00
acpiwmibus at acpiwmi0 not configured
ACPI: Enabled 2 GPEs in block 00 to 1F
attimer1: attached to pcppi1
pckbdprobe: reset error 5
pmsprobe: reset error 5
pci0 at mainbus0 bus 0: configuration mode 1
acpi0: MCFG: 000:00:0: Ok (cfg[0x100]=0x14801022 extconf=Y)
acpi0: MCFG: 000:00:2: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:00:2: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:01:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:01:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:01:1: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 000:01:2: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 000:02:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:02:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:03:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:03:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:03:1: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 000:04:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:04:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:05:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:05:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:07:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:07:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:07:1: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 000:08:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:08:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:08:1: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 000:20:0: invalid config space (cfg[0x100]=0x790b1022, alias=true)
acpi0: MCFG: 000:20:0: Ok (cfg[0x100]=0x790b1022 extconf=N)
acpi0: MCFG: 000:20:3: invalid config space (cfg[0x100]=0x790e1022, alias=true)
acpi0: MCFG: 000:20:3: Ok (cfg[0x100]=0x790e1022 extconf=N)
acpi0: MCFG: 000:24:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:1: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:1: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:2: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:2: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:3: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:3: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:4: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:4: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:5: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:5: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:6: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:6: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: 000:24:7: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 000:24:7: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: bus 0: valid devices
acpi0: MCFG: 000:00:0
acpi0: MCFG: 000:00:2
acpi0: MCFG: 000:01:0
acpi0: MCFG: 000:01:1
acpi0: MCFG: 000:01:2
acpi0: MCFG: 000:02:0
acpi0: MCFG: 000:03:0
acpi0: MCFG: 000:03:1
acpi0: MCFG: 000:04:0
acpi0: MCFG: 000:05:0
acpi0: MCFG: 000:07:0
acpi0: MCFG: 000:07:1
acpi0: MCFG: 000:08:0
acpi0: MCFG: 000:08:1
acpi0: MCFG: 000:20:0
acpi0: MCFG: 000:20:3
acpi0: MCFG: 000:24:0
acpi0: MCFG: 000:24:1
acpi0: MCFG: 000:24:2
acpi0: MCFG: 000:24:3
acpi0: MCFG: 000:24:4
acpi0: MCFG: 000:24:5
acpi0: MCFG: 000:24:6
acpi0: MCFG: 000:24:7
acpi0: acpimcfg_map_bus done
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
amdsmn0 at pci0 dev 0 function 0: AMD System Management Network
amdzentemp0 at amdsmn0: AMD CPU Temperature Sensors (Family17h)
AMD Family17h/7xh IOMMU (IOMMU system) at pci0 dev 0 function 2 not configured
pchb0 at pci0 dev 1 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb0 at pci0 dev 1 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb0: PCI Express capability version 2 x8 @ 8.0GT/s
ppb0: link is x4 @ 8.0GT/s
pci1 at ppb0 bus 1
acpi0: MCFG: 001:00:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 001:00:1: Ok (cfg[0x100]=0x00010001 extconf=Y)
acpi0: MCFG: 001:00:2: Ok (cfg[0x100]=0x00010001 extconf=Y)
acpi0: MCFG: bus 1: valid devices
acpi0: MCFG: 001:00:0
acpi0: MCFG: 001:00:1
acpi0: MCFG: 001:00:2
acpi0: acpimcfg_map_bus done
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
xhci0 at pci1 dev 0 function 0: AMD product 43b9 (rev. 0x02)
xhci0: 64-bit DMA
allocated pic msi0 type edge pin 0 level 6 to cpu0 slot 16 idt entry 97
xhci0: interrupting at msi0 vec 0
xhci0: xHCI version 1.10
xhci0: hcs1=1600087f hcs2=fc0000fa hcs3=200000a
xhci0: hcc=0x200ef81
xhci0: xECP 800
xhci0: hcc2=0x3f
xhci0: ECR: 0x00000801
xhci0: ECR: 0x03100802
xhci0: SP: 0x03100802 0x20425355 0x00000201 0x00000000
xhci0: ss ports 1 – 2
xhci0: ECR: 0x03000802
xhci0: SP: 0x03000802 0x20425355 0x00000603 0x00000000
xhci0: ss ports 3 – 8
xhci0: ECR: 0x02000802
xhci0: SP: 0x02000802 0x20425355 0x00190e09 0x00000000
xhci0: hs ports 9 – 22
xhci0: ECR: 0x0000000a
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x0000007f
xhci0: sc_maxports 22
xhci0: sc_maxspbuf 31
xhci0: eventst: 0x000000013e8c8fc0 0xffffde085af10fc0 1000
xhci0: dcbaa: 0x000000013e8c9000 0xffffde085af11000 1000
xhci0: current IMOD 0
xhci0: USBCMD 0x00000005
usb0 at xhci0: USB revision 3.1
usb1 at xhci0: USB revision 2.0
ahcisata0 at pci1 dev 0 function 1: AMD product 43b5 (rev. 0x02)
ahcisata0: 64-bit DMA
ahcisata0: AHCI revision 1.31, 8 ports, 32 slots, CAP 0xef36ff27
allocated pic msi1 type edge pin 0 level 6 to cpu0 slot 17 idt entry 98
ahcisata0: interrupting at msi1 vec 0
atabus0 at ahcisata0 channel 0
atabus1 at ahcisata0 channel 1
atabus2 at ahcisata0 channel 2
atabus3 at ahcisata0 channel 3
atabus4 at ahcisata0 channel 4
atabus5 at ahcisata0 channel 5
atabus6 at ahcisata0 channel 6
atabus7 at ahcisata0 channel 7
ppb1 at pci1 dev 0 function 2: AMD product 43b0 (rev. 0x02)
ppb1: PCI Express capability version 2
pci2 at ppb1 bus 2
acpi0: MCFG: 002:00:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 002:01:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 002:02:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 002:03:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 002:04:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 002:06:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: 002:07:0: Ok (cfg[0x100]=0x20010001 extconf=Y)
acpi0: MCFG: bus 2: valid devices
acpi0: MCFG: 002:00:0
acpi0: MCFG: 002:01:0
acpi0: MCFG: 002:02:0
acpi0: MCFG: 002:03:0
acpi0: MCFG: 002:04:0
acpi0: MCFG: 002:06:0
acpi0: MCFG: 002:07:0
acpi0: acpimcfg_map_bus done
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
ppb2 at pci2 dev 0 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb2: PCI Express capability version 2 x1 @ 5.0GT/s
pci3 at ppb2 bus 3
acpi0: MCFG: bus 3: no valid devices.
acpi0: acpimcfg_map_bus done
pci3: i/o space, memory space enabled, rd/line, wr/inv ok
ppb3 at pci2 dev 1 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb3: PCI Express capability version 2 x1 @ 5.0GT/s
ppb3: link is x1 @ 2.5GT/s
pci4 at ppb3 bus 4
acpi0: MCFG: 004:00:0: invalid config space (cfg[0x100]=0x00000000, alias=false)
acpi0: MCFG: 004:00:0: Ok (cfg[0x100]=0x00000000 extconf=N)
acpi0: MCFG: bus 4: valid devices
acpi0: MCFG: 004:00:0
acpi0: acpimcfg_map_bus done
pci4: i/o space, memory space enabled, rd/line, wr/inv ok
ppb4 at pci4 dev 0 function 0: ASMedia ASM1083/1085 PCIe-PCI Bridge (rev. 0x03)
pci5 at ppb4 bus 5
acpi0: MCFG: bus 5: no valid devices.
acpi0: acpimcfg_map_bus done
pci5: i/o space, memory space enabled, rd/line, wr/inv ok
ppb5 at pci2 dev 2 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb5: PCI Express capability version 2 x1 @ 5.0GT/s
pci6 at ppb5 bus 6
acpi0: MCFG: bus 6: no valid devices.
acpi0: acpimcfg_map_bus done
pci6: i/o space, memory space enabled, rd/line, wr/inv ok
ppb6 at pci2 dev 3 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb6: PCI Express capability version 2 x1 @ 5.0GT/s
pci7 at ppb6 bus 7
acpi0: MCFG: bus 7: no valid devices.
acpi0: acpimcfg_map_bus done
pci7: i/o space, memory space enabled, rd/line, wr/inv ok
ppb7 at pci2 dev 4 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb7: PCI Express capability version 2 x2 @ 5.0GT/s
pci8 at ppb7 bus 8
acpi0: MCFG: 008:00:0: Ok (cfg[0x100]=0x15020001 extconf=Y)
acpi0: MCFG: bus 8: valid devices
acpi0: MCFG: 008:00:0
acpi0: acpimcfg_map_bus done
pci8: i/o space, memory space enabled, rd/line, wr/inv ok
aq0 at pci8 dev 0 function 0: Aquantia AQC100 10 Gigabit Network Adapter (rev. 0x02)
aq0: FLB> MAC kickstart done, 311 ms
aq0: FLB> F/W restart: 10 ms
aq0: FLB> F/W successfully loaded from flash.
aq0: ncpu=12, pci_msix_count=32. allocate 16 interrupts for 8*2 queues
allocated pic msix2 type edge pin 0 level 6 to cpu0 slot 18 idt entry 99
allocated pic msix2 type edge pin 1 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 2 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 3 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 4 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 5 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 6 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 7 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 8 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 9 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 10 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 11 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 12 level 6 to cpu0 slot 19 idt entry 100
allocated pic msix2 type edge pin 13 level 6 to cpu0 slot 20 idt entry 101
allocated pic msix2 type edge pin 14 level 6 to cpu0 slot 20 idt entry 101
allocated pic msix2 type edge pin 15 level 6 to cpu0 slot 20 idt entry 101
aq0: Atlantic revision B1, F/W version 3.1.58
aq0: fw2x> F/W capabilities=0x63c0001900007f20
aq0: Etheraddr: xx:xx:xx:xx:xx:xx
ppb8 at pci2 dev 6 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb8: PCI Express capability version 2 x1 @ 5.0GT/s
pci9 at ppb8 bus 9
acpi0: MCFG: bus 9: no valid devices.
acpi0: acpimcfg_map_bus done
pci9: i/o space, memory space enabled, rd/line, wr/inv ok
ppb9 at pci2 dev 7 function 0: AMD 300 Series PCIe (rev. 0x02)
ppb9: PCI Express capability version 2 x1 @ 5.0GT/s
ppb9: link is x1 @ 2.5GT/s
pci10 at ppb9 bus 10
acpi0: MCFG: 010:00:0: Ok (cfg[0x100]=0x14010001 extconf=Y)
acpi0: MCFG: bus 10: valid devices
acpi0: MCFG: 010:00:0
acpi0: acpimcfg_map_bus done
pci10: i/o space, memory space enabled, rd/line, wr/inv ok
athn0 at pci10 dev 0 function 0allocated pic ioapic1 type level pin 3 level 6 to cpu0 slot 2 idt entry 101
: Atheros AR9287
athn0: rev 2 (2T2R), ROM rev 4, address xx:xx:xx:xx:xx:xx
athn0: interrupting at ioapic1 pin 3
athn0: 11b rates: 1Mbps 2Mbps 5.5Mbps 11Mbps
athn0: 11g rates: 1Mbps 2Mbps 5.5Mbps 11Mbps 6Mbps 9Mbps 12Mbps 18Mbps 24Mbps 36Mbps 48Mbps 54Mbps
ppb10 at pci0 dev 1 function 2: AMD 17h/7xh PCIe (rev. 0x00)
ppb10: PCI Express capability version 2 x4 @ 8.0GT/s
pci11 at ppb10 bus 11
acpi0: MCFG: 011:00:0: Ok (cfg[0x100]=0x15020001 extconf=Y)
acpi0: MCFG: bus 11: valid devices
acpi0: MCFG: 011:00:0
acpi0: acpimcfg_map_bus done
pci11: i/o space, memory space enabled, rd/line, wr/inv ok
nvme0 at pci11 dev 0 function 0: Western Digital (SanDisk) product 5019 (rev. 0x01)
nvme0: NVMe 1.4
allocated pic msix3 type edge pin 0 level 6 to cpu0 slot 20 idt entry 101
nvme0: for admin queue interrupting at msix3 vec 0
nvme0: WDC WDS100T2B0C-00PXH0, firmware 233010WD, serial 21281W452002
allocated pic msix3 type edge pin 1 level 6 to cpu0 slot 21 idt entry 102
nvme0: for io queue 1 interrupting at msix3 vec 1 affinity to cpu0
allocated pic msix3 type edge pin 2 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 2 interrupting at msix3 vec 2 affinity to cpu1
allocated pic msix3 type edge pin 3 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 3 interrupting at msix3 vec 3 affinity to cpu2
allocated pic msix3 type edge pin 4 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 4 interrupting at msix3 vec 4 affinity to cpu3
allocated pic msix3 type edge pin 5 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 5 interrupting at msix3 vec 5 affinity to cpu4
allocated pic msix3 type edge pin 6 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 6 interrupting at msix3 vec 6 affinity to cpu5
allocated pic msix3 type edge pin 7 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 7 interrupting at msix3 vec 7 affinity to cpu6
allocated pic msix3 type edge pin 8 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 8 interrupting at msix3 vec 8 affinity to cpu7
allocated pic msix3 type edge pin 9 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 9 interrupting at msix3 vec 9 affinity to cpu8
allocated pic msix3 type edge pin 10 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 10 interrupting at msix3 vec 10 affinity to cpu9
allocated pic msix3 type edge pin 11 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 11 interrupting at msix3 vec 11 affinity to cpu10
allocated pic msix3 type edge pin 12 level 6 to cpu0 slot 22 idt entry 103
nvme0: for io queue 12 interrupting at msix3 vec 12 affinity to cpu11
ld0 at nvme0 nsid 1
ld0: 931 GB, 121601 cyl, 255 head, 63 sec, 512 bytes/sect x 1953525168 sectors
pchb1 at pci0 dev 2 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb2 at pci0 dev 3 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb11 at pci0 dev 3 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb11: PCI Express capability version 2 x16 @ 8.0GT/s
ppb11: link is x8 @ 8.0GT/s
pci12 at ppb11 bus 12
acpi0: MCFG: 012:00:0: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 012:00:1: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: bus 12: valid devices
acpi0: MCFG: 012:00:0
acpi0: MCFG: 012:00:1
acpi0: acpimcfg_map_bus done
pci12: i/o space, memory space enabled, rd/line, wr/inv ok
amdgpu0 at pci12 dev 0 function 0: ATI Technologies Radeon RX 460/560D / Pro 450/455/460/555/555X/560/560X (rev. 0xcf)
amdgpu0: WARNING: power management not supported
hdaudio0 at pci12 dev 0 function 1: HD Audio Controller
allocated pic msi4 type edge pin 0 level 7 to cpu0 slot 22 idt entry 112
hdaudio0: interrupting at msi4 vec 0
hdaudio0: HDA ver. 1.0, OSS 5, ISS 0, BSS 0, SDO 1, 64-bit
hdafg0 at hdaudio0 vendor 0x1002 product 0xAA01 nid 0x01: ATI R6xx HDMI
hdafg0: HDMI00 2ch: Digital Out [Jack]
nid=03 [pin: Digital Out (Jack)]
nid=02 [source: dac]
hdafg0: HDMI01 2ch: Digital Out [Jack]
nid=05 [pin: Digital Out (Jack)]
nid=04 [source: dac]
hdafg0: HDMI02 2ch: Digital Out [Jack]
nid=07 [pin: Digital Out (Jack)]
nid=06 [source: dac]
hdafg0: HDMI03 2ch: Digital Out [Jack]
nid=09 [pin: Digital Out (Jack)]
nid=08 [source: dac]
hdafg0: HDMI04 2ch: Digital Out [Jack]
nid=0B [pin: Digital Out (Jack)]
nid=0A [source: dac]
hdafg0: 2ch/0ch 32000Hz 44100Hz 48000Hz PCM16 AC3
audio0 at hdafg0: playback
audio0: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
spkr1 at audio0: PC Speaker (synthesized)
wsbell at spkr1 not configured
pchb3 at pci0 dev 4 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb4 at pci0 dev 5 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
pchb5 at pci0 dev 7 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb12 at pci0 dev 7 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb12: PCI Express capability version 2 x16 @ 16.0GT/s
pci13 at ppb12 bus 13
acpi0: MCFG: 013:00:0: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: bus 13: valid devices
acpi0: MCFG: 013:00:0
acpi0: acpimcfg_map_bus done
pci13: i/o space, memory space enabled, rd/line, wr/inv ok
AMD product 148a (non-essential instrumentation, subclass 0x00) at pci13 dev 0 function 0 not configured
pchb6 at pci0 dev 8 function 0: AMD 17h/7xh Host Bridge (rev. 0x00)
ppb13 at pci0 dev 8 function 1: AMD 17h/7xh PCIe (rev. 0x00)
ppb13: PCI Express capability version 2 x16 @ 16.0GT/s
pci14 at ppb13 bus 14
acpi0: MCFG: 014:00:0: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 014:00:1: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 014:00:3: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: 014:00:4: Ok (cfg[0x100]=0x1501000b extconf=Y)
acpi0: MCFG: bus 14: valid devices
acpi0: MCFG: 014:00:0
acpi0: MCFG: 014:00:1
acpi0: MCFG: 014:00:3
acpi0: MCFG: 014:00:4
acpi0: acpimcfg_map_bus done
pci14: i/o space, memory space enabled, rd/line, wr/inv ok
AMD Family17h/7xh Reserved SPP (non-essential instrumentation, subclass 0x00) at pci14 dev 0 function 0 not configured
amdccp0 at pci14 dev 0 function 1: AMD Cryptographic Coprocessor
xhci1 at pci14 dev 0 function 3: AMD Family17h/7xh USB 3.0 Host Controller (rev. 0x00)
xhci1: 64-bit DMA
allocated pic msix5 type edge pin 0 level 6 to cpu0 slot 23 idt entry 103
xhci1: interrupting at msix5 vec 0
xhci1: xHCI version 1.10
xhci1: hcs1=8000840 hcs2=140000f1 hcs3=200000a
xhci1: hcc=0x278ffe5
xhci1: xECP 9e0
xhci1: hcc2=0x3f
xhci1: ECR: 0x00000401
xhci1: ECR: 0x02000402
xhci1: SP: 0x02000402 0x20425355 0x00180401 0x00000000
xhci1: hs ports 1 – 4
xhci1: ECR: 0x03100802
xhci1: SP: 0x03100802 0x20425355 0x10000105 0x00000000
xhci1: ss ports 5 – 5
xhci1: ECR: 0x03100802
xhci1: SP: 0x03100802 0x20425355 0x10000106 0x00000000
xhci1: ss ports 6 – 6
xhci1: ECR: 0x03100802
xhci1: SP: 0x03100802 0x20425355 0x10000107 0x00000000
xhci1: ss ports 7 – 7
xhci1: ECR: 0x03100802
xhci1: SP: 0x03100802 0x20425355 0x10000108 0x00000000
xhci1: ss ports 8 – 8
xhci1: ECR: 0x000f000a
xhci1: PAGESIZE 0x00000001
xhci1: sc_pgsz 0x00001000
xhci1: sc_maxslots 0x00000040
xhci1: sc_maxports 8
xhci1: sc_maxspbuf 2
xhci1: eventst: 0x00000001409d0fc0 0xffffde085b6a1fc0 1000
xhci1: dcbaa: 0x00000001409d1000 0xffffde085b6a2000 1000
xhci1: current IMOD 0
xhci1: USBCMD 0x00000005
usb2 at xhci1: USB revision 3.1
usb3 at xhci1: USB revision 2.0
hdaudio1 at pci14 dev 0 function 4: HD Audio Controller
allocated pic msi6 type edge pin 0 level 7 to cpu0 slot 24 idt entry 113
hdaudio1: interrupting at msi6 vec 0
hdaudio1: HDA ver. 1.0, OSS 4, ISS 4, BSS 0, SDO 1, 64-bit
hdafg1 at hdaudio1 vendor 0x10EC product 0x0892 nid 0x01: Realtek ALC892
hdafg1: DAC00 8ch: Speaker [Jack]
nid=14 [pin: Speaker (Green Jack)]
nid=0C [source: dac, record]
nid=02 [source: dac]
nid=0B [source: record]
nid=16 [pin: Speaker (Orange Jack)]
nid=0E [source: dac, record]
nid=04 [source: dac]
nid=0B [source: record]
nid=15 [pin: Speaker (Black Jack)]
nid=0D [source: dac, record]
nid=03 [source: dac]
nid=0B [source: record]
nid=17 [pin: Speaker (Grey Jack)]
nid=0F [source: dac, record]
nid=05 [source: dac]
nid=0B [source: record]
hdafg1: DAC01 2ch: HP Out [Jack]
nid=1B [pin: HP Out (Green Jack)]
nid=26 [source: dac, record]
nid=25 [source: dac]
nid=0B [source: record]
hdafg1: DIG02 2ch: SPDIF Out [Jack]
nid=1E [pin: SPDIF Out (Black Jack)]
nid=06 [source: dac]
hdafg1: ADC03 2ch: Line In [Jack], Mic In [Jack]
nid=18 [pin: Mic In (Pink Jack)]
nid=1A [pin: Line In (Blue Jack)]
hdafg1: ADC04 2ch: Mic In [Jack]
nid=19 [pin: Mic In (Pink Jack)]
hdafg1: 8ch/2ch 32000Hz 44100Hz 48000Hz 88200Hz 96000Hz 192000Hz PCM16 PCM20 PCM24 AC3
audio1 at hdafg1: playback, capture, full duplex, independent
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for playback
audio1: slinear_le:16 2ch 48000Hz, blk 1920 bytes (10ms) for recording
spkr2 at audio1: PC Speaker (synthesized)
wsbell at spkr2 not configured
piixpm0 at pci0 dev 20 function 0: AMD X370/X399 SMBus Controller (rev. 0x61)
piixpm0: SMBus @ 0x0b00
piixpm0: interrupting at SMI,
iic0 at piixpm0 port 0: I2C bus
iic1 at piixpm0 port 1: I2C bus
pcib0 at pci0 dev 20 function 3: AMD FCH LPC (rev. 0x51)
pchb7 at pci0 dev 24 function 0: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb8 at pci0 dev 24 function 1: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb9 at pci0 dev 24 function 2: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb10 at pci0 dev 24 function 3: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb11 at pci0 dev 24 function 4: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb12 at pci0 dev 24 function 5: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb13 at pci0 dev 24 function 6: AMD 17h/7xh Data Fabric (rev. 0x00)
pchb14 at pci0 dev 24 function 7: AMD 17h/7xh Data Fabric (rev. 0x00)
isa0 at pcib0
acpicpu0 at cpu0: ACPI CPU
acpicpu0: C1: FFH, lat 1 us, pow 0 mW
acpicpu0: C2: I/O, lat 18 us, pow 0 mW
acpicpu0: P0: FFH, lat 1 us, pow 3960 mW, 3600 MHz
acpicpu0: P1: FFH, lat 1 us, pow 2800 mW, 2800 MHz
acpicpu0: P2: FFH, lat 1 us, pow 1980 mW, 2200 MHz
acpicpu0: T0: I/O, lat 1 us, pow 0 mW, 100 %
acpicpu0: T1: I/O, lat 1 us, pow 0 mW, 88 %
acpicpu0: T2: I/O, lat 1 us, pow 0 mW, 76 %
acpicpu0: T3: I/O, lat 1 us, pow 0 mW, 64 %
acpicpu0: T4: I/O, lat 1 us, pow 0 mW, 52 %
acpicpu0: T5: I/O, lat 1 us, pow 0 mW, 40 %
acpicpu0: T6: I/O, lat 1 us, pow 0 mW, 28 %
acpicpu0: T7: I/O, lat 1 us, pow 0 mW, 16 %
acpicpu0: id 0, lapic id 0, cap 0x0000, flags 0x00114a57
acpicpu0: C-state coordination: 2 CPUs, domain 0, type HW_ALL
acpicpu0: P-state coordination: 2 CPUs, domain 0, type HW_ALL
acpicpu1 at cpu1: ACPI CPU
acpicpu1: id 2, lapic id 2, cap 0x0000, flags 0x00114a57
acpicpu1: C-state coordination: 2 CPUs, domain 1, type HW_ALL
acpicpu1: P-state coordination: 2 CPUs, domain 1, type HW_ALL
acpicpu2 at cpu2: ACPI CPU
acpicpu2: id 4, lapic id 4, cap 0x0000, flags 0x00114a57
acpicpu2: C-state coordination: 2 CPUs, domain 2, type HW_ALL
acpicpu2: P-state coordination: 2 CPUs, domain 2, type HW_ALL
acpicpu3 at cpu3: ACPI CPU
acpicpu3: id 6, lapic id 8, cap 0x0000, flags 0x00114a57
acpicpu3: C-state coordination: 2 CPUs, domain 3, type HW_ALL
acpicpu3: P-state coordination: 2 CPUs, domain 3, type HW_ALL
acpicpu4 at cpu4: ACPI CPU
acpicpu4: id 8, lapic id 10, cap 0x0000, flags 0x00114a57
acpicpu4: C-state coordination: 2 CPUs, domain 4, type HW_ALL
acpicpu4: P-state coordination: 2 CPUs, domain 4, type HW_ALL
acpicpu5 at cpu5: ACPI CPU
acpicpu5: id 10, lapic id 12, cap 0x0000, flags 0x00114a57
acpicpu5: C-state coordination: 2 CPUs, domain 5, type HW_ALL
acpicpu5: P-state coordination: 2 CPUs, domain 5, type HW_ALL
acpicpu6 at cpu6: ACPI CPU
acpicpu6: id 1, lapic id 1, cap 0x0000, flags 0x00114a57
acpicpu6: C-state coordination: 2 CPUs, domain 0, type HW_ALL
acpicpu6: P-state coordination: 2 CPUs, domain 0, type HW_ALL
acpicpu7 at cpu7: ACPI CPU
acpicpu7: id 3, lapic id 3, cap 0x0000, flags 0x00114a57
acpicpu7: C-state coordination: 2 CPUs, domain 1, type HW_ALL
acpicpu7: P-state coordination: 2 CPUs, domain 1, type HW_ALL
acpicpu8 at cpu8: ACPI CPU
acpicpu8: id 5, lapic id 5, cap 0x0000, flags 0x00114a57
acpicpu8: C-state coordination: 2 CPUs, domain 2, type HW_ALL
acpicpu8: P-state coordination: 2 CPUs, domain 2, type HW_ALL
acpicpu9 at cpu9: ACPI CPU
acpicpu9: id 7, lapic id 9, cap 0x0000, flags 0x00114a57
acpicpu9: C-state coordination: 2 CPUs, domain 3, type HW_ALL
acpicpu9: P-state coordination: 2 CPUs, domain 3, type HW_ALL
acpicpu10 at cpu10: ACPI CPU
acpicpu10: id 9, lapic id 11, cap 0x0000, flags 0x00114a57
acpicpu10: C-state coordination: 2 CPUs, domain 4, type HW_ALL
acpicpu10: P-state coordination: 2 CPUs, domain 4, type HW_ALL
acpicpu11 at cpu11: ACPI CPU
acpicpu11: id 11, lapic id 13, cap 0x0000, flags 0x00114a57
acpicpu11: C-state coordination: 2 CPUs, domain 5, type HW_ALL
acpicpu11: P-state coordination: 2 CPUs, domain 5, type HW_ALL
SRAT: 0 NUMA nodes
Initializing SSP: 117af377eee5efa2 749900ef01a5cf26 74ca3f4a78918ebb eaacdd8292dfd162 18ad8a57aedcc1ed aef2dba1325dfc65 4208c3df311185f4 89880567fff3e805
cpu0: TSC freq from HPET 3593254000 Hz
cpu0: [re]calibrating local timer
cpu0: apic clock running at 99 MHz
timecounter: Timecounter “lapic” frequency 99813000 Hz quality -100
timecounter: Timecounter “clockinterrupt” frequency 100 Hz quality 0
UVM: using package allocation scheme, 1 package(s) per bucket
cpu1: TSC skew=0 drift=0
cpu1: running
cpu2: TSC skew=0 drift=0
cpu2: running
cpu3: TSC skew=0 drift=0
cpu3: running
cpu4: running
cpu4: TSC skew=0 drift=0
cpu5: TSC skew=0 drift=0
cpu5: running
cpu6: TSC skew=0 drift=0
cpu6: running
cpu7: running
cpu7: TSC skew=0 drift=0
cpu8: TSC skew=0 drift=0
cpu8: running
cpu9: TSC skew=0 drift=0
cpu9: running
cpu10: TSC skew=0 drift=0
cpu10: running
cpu11: TSC skew=0 drift=0
cpu11: running
timecounter: Timecounter “TSC” frequency 3593254000 Hz quality 3000
uhub0 at usb0: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub0: 8 ports with 8 removable, self powered
uhub1 at usb1: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub1: 14 ports with 14 removable, self powered
uhub2 at usb2: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 3.00/1.00, addr 0
uhub2: 4 ports with 4 removable, self powered
uhub3 at usb3: NetBSD (0x0000) xHCI root hub (0x0000), class 9/0, rev 2.00/1.00, addr 0
uhub3: 4 ports with 4 removable, self powered
acpicpu11: ACPI CPUs started
ld0: GPT GUID: 9b94f472-237d-4601-b411-c7262ae07e17
dk0 at ld0: “17abe03b-7c17-44cc-8dac-d3d56968b6b1”, 262144 blocks at 2048, type: msdos
dk1 at ld0: “c072c1e3-5d0b-4bd4-8789-7370295360e1”, 134897664 blocks at 264192, type: ffs
dk2 at ld0: “0291617a-ffbb-457e-b908-af9f61e5790f”, 67010560 blocks at 135161856, type: swap
dk3 at ld0: “ca370a40-b6d3-4b0a-9270-00acc6df4e2b”, 419430400 blocks at 202172416, type: ffs
dk4 at ld0: “8ae92095-2b67-450a-b3ac-32c912b78f08”, 1331922319 blocks at 621602816, type: ffs
IPsec: Initialized Security Association Processing.
aes: Intel AES-NI
chacha: x86 SSE2 ChaCha
adiantum: self-test passed
aes_ccm: self-test passed
blake2s: self-test passed
ahcisata0 port 0: device present, speed: 6.0Gb/s
ahcisata0 port 5: device present, speed: 1.5Gb/s
ahcisata0 port 1: device present, speed: 3.0Gb/s
wd0 at atabus0 drive 0
wd0:
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 476 GB, 992277 cyl, 16 head, 63 sec, 512 bytes/sect x 1000215216 sectors
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133), WRITE DMA FUA, NCQ (32 tags)
wd0(ahcisata0:0:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA), NCQ (31 tags)
wd1 at atabus1 drive 0
wd1:
wd1: drive supports 16-sector PIO transfers, LBA48 addressing
wd1: 149 GB, 310101 cyl, 16 head, 63 sec, 512 bytes/sect x 312581808 sectors
wd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 7, NCQ (32 tags)
wd1(ahcisata0:1:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133) (using DMA), NCQ (31 tags)
uhub4 at uhub1 port 11: SMSC (0x0424) product 2504 (0x2504), class 9/0, rev 2.00/0.01, addr 1
uhub4: multiple transaction translators
uhub4: 2 ports with 2 removable, self powered
uhidev0 at uhub3 port 1 configuration 1 interface 0
uhidev0: vendor 20bc (0x20bc) Canyon controller GPW6 (0x2282), rev 2.00/2.01, addr 1, iclass 3/0
uhid0 at uhidev0: input=27, output=4, feature=0
ubt0 at uhub3 port 2
ubt0: Cambridge Silicon Radio (0x0a12) BT DONGLE10 (0x0001), rev 2.00/88.91, addr 2
atapibus0 at atabus5: 1 targets
cd0 at atapibus0 drive 0: cdrom removable
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100)
cd0(ahcisata0:5:0): using PIO mode 4, DMA mode 2, Ultra-DMA mode 5 (Ultra/100) (using DMA)
crypto: assign driver 0, flags 2
crypto: driver 0 registers alg 1 flags 0 maxoplen 0
crypto: driver 0 registers alg 2 flags 0 maxoplen 0
crypto: driver 0 registers alg 3 flags 0 maxoplen 0
crypto: driver 0 registers alg 4 flags 0 maxoplen 0
crypto: driver 0 registers alg 5 flags 0 maxoplen 0
crypto: driver 0 registers alg 26 flags 0 maxoplen 0
crypto: driver 0 registers alg 27 flags 0 maxoplen 0
crypto: driver 0 registers alg 29 flags 0 maxoplen 0
crypto: driver 0 registers alg 33 flags 0 maxoplen 0
crypto: driver 0 registers alg 17 flags 0 maxoplen 0
crypto: driver 0 registers alg 6 flags 0 maxoplen 0
crypto: driver 0 registers alg 19 flags 0 maxoplen 0
crypto: driver 0 registers alg 7 flags 0 maxoplen 0
crypto: driver 0 registers alg 20 flags 0 maxoplen 0
crypto: driver 0 registers alg 15 flags 0 maxoplen 0
crypto: driver 0 registers alg 24 flags 0 maxoplen 0
crypto: driver 0 registers alg 25 flags 0 maxoplen 0
crypto: driver 0 registers alg 8 flags 0 maxoplen 0
crypto: driver 0 registers alg 21 flags 0 maxoplen 0
crypto: driver 0 registers alg 16 flags 0 maxoplen 0
crypto: driver 0 registers alg 9 flags 0 maxoplen 0
crypto: driver 0 registers alg 10 flags 0 maxoplen 0
crypto: driver 0 registers alg 13 flags 0 maxoplen 0
crypto: driver 0 registers alg 14 flags 0 maxoplen 0
crypto: driver 0 registers alg 28 flags 0 maxoplen 0
crypto: driver 0 registers alg 30 flags 0 maxoplen 0
crypto: driver 0 registers alg 31 flags 0 maxoplen 0
crypto: driver 0 registers alg 32 flags 0 maxoplen 0
crypto: driver 0 registers alg 11 flags 0 maxoplen 0
crypto: driver 0 registers alg 18 flags 0 maxoplen 0
crypto: driver 0 registers alg 23 flags 0 maxoplen 0
crypto: driver 0 registers alg 22 flags 0 maxoplen 0
cgd: self-test aes-xts-256
cgd: self-test aes-xts-512
cgd: self-test aes-cbc-128
cgd: self-test aes-cbc-256
cgd: self-test 3des-cbc-192
cgd: self-test blowfish-cbc-448
cgd: self-test aes-cbc-128 (encblkno8)
cgd: self-tests passed
swwdog0: software watchdog initialized
Searching for RAID components…
WARNING: 2 errors while detecting hardware; check system log.
boot device: ld0
root on dk1 dumps on dk2
root file system type: ffs
kern.module.path=/stand/amd64/10.0/modules
[drm] initializing kernel modesetting (POLARIS11 0x1002:0x67EF 0x1043:0x04B8 0xCF).
[drm] register mmio base: 0xFCB00000
[drm] register mmio size: 262144
pci_io_find: expected type i/o, found mem
pci_io_find: expected type i/o, found mem
pci_io_find: expected type i/o, found mem
pci_io_find: expected type i/o, found mem
[drm] PCI I/O BAR is not found.
[drm] add ip block number 0
[drm] add ip block number 1
[drm] add ip block number 2
[drm] add ip block number 3
[drm] add ip block number 4
[drm] add ip block number 5
[drm] add ip block number 6
[drm] add ip block number 7
[drm] add ip block number 8
ATOM BIOS: 115-C994PI00-100
[drm] UVD is enabled in VM mode
[drm] UVD ENC is enabled in VM mode
[drm] VCE enabled in VM mode
[drm] vm size is 128 GB, 2 levels, block size is 10-bit, fragment size is 9-bit
amdgpu0: VRAM: 2048M 0x000000F400000000 – 0x000000F47FFFFFFF (2048M used)
amdgpu0: GART: 256M 0x000000FF00000000 – 0x000000FF0FFFFFFF
[drm] Detected VRAM RAM=2048M, BAR=256M
[drm] RAM width 128bits GDDR5
Zone kernel: Available graphics memory: 9007199253306146 KiB
Zone dma32: Available graphics memory: 2097152 KiB
[drm] amdgpu: 2048M of VRAM memory ready
[drm] amdgpu: 3072M of GTT memory ready.
[drm] GART: num cpu pages 65536, num gpu pages 65536
[drm] PCIE GART of 256M enabled (table at 0x000000F400300000).
amdgpu0: debug: amdgpu: using MSI/MSI-X.
[drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[drm] Driver supports precise vblank timestamp query.
allocated pic msi7 type edge pin 0 level 6 to cpu0 slot 30 idt entry 104
amdgpu0: interrupting at msi7 vec 0 (amdgpu0)
[drm] Chained IB support enabled!
hwmgr_sw_init smu backed is polaris10_smu
powerplay sw init successfully
[drm] AMDGPU Display Connectors
[drm] Connector 0:
[drm] DP-1
[drm] HPD5
[drm] DDC: 0x4868 0x4868 0x4869 0x4869 0x486a 0x486a 0x486b 0x486b
[drm] Encoders:
[drm] DFP1: INTERNAL_UNIPHY1
[drm] Connector 1:
[drm] HDMI-A-1
[drm] HPD3
[drm] DDC: 0x4874 0x4874 0x4875 0x4875 0x4876 0x4876 0x4877 0x4877
[drm] Encoders:
[drm] DFP2: INTERNAL_UNIPHY1
[drm] Connector 2:
[drm] DVI-D-1
[drm] HPD4
[drm] DDC: 0x4878 0x4878 0x4879 0x4879 0x487a 0x487a 0x487b 0x487b
[drm] Encoders:
[drm] DFP3: INTERNAL_UNIPHY
[drm] Found UVD firmware Version: 1.130 Family ID: 16
[drm] Found VCE firmware Version: 35.1a Binary ID: 3
Can’t find requested voltage id in vdd_dep_on_sclk table
message 308 was not supported
last message was not supported
{drm:netbsd:dce_v11_0_pageflip_irq+0xf2} amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
{drm:netbsd:dce_v11_0_pageflip_irq+0xf2} amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
[drm] UVD and UVD ENC initialized successfully.
[drm] VCE initialized successfully.
amdgpufb0 at amdgpu0
[drm] Initialized amdgpu 3.36.0 20150101 for amdgpu0 on minor 0
amdgpufb0: framebuffer at 0xd0830000, size 1920×1080, depth 32, stride 7680
{drm:netbsd:dce_v11_0_pageflip_irq+0xf2} amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
{drm:netbsd:dce_v11_0_pageflip_irq+0xf2} amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
max_dotclock according to supported modes: 148500
wsdisplay0 at amdgpufb0 kbdmux 1: console (default, vt100 emulation)
wsmux1: connecting to wsdisplay0
aq0: link is UP: speed=10000
max_dotclock according to supported modes: 148500
wsdisplay0: screen 1 added (default, vt100 emulation)
max_dotclock according to supported modes: 148500
wsdisplay0: screen 2 added (default, vt100 emulation)
max_dotclock according to supported modes: 148500
wsdisplay0: screen 3 added (default, vt100 emulation)
max_dotclock according to supported modes: 148500
wsdisplay0: screen 4 added (default, vt100 emulation)
uhub5 at uhub1 port 2: VIA Labs, Inc. (0x2109) USB2.0 Hub (0x2817), class 9/0, rev 2.10/90.23, addr 2
uhub5: multiple transaction translators
uhub5: 4 ports with 4 removable, self powered
uaudio0 at uhub5 port 1 configuration 1 interface 0
uaudio0: C-Media Electronics Inc. (0x0d8c) Genesis Radium 100 (0x0014), rev 1.10/1.00, addr 3
uaudio0: audio rev 1.00
uaudio0: 5 mixer controls
audio2 at uaudio0: playback, capture, full duplex, independent
audio2: slinear_le:16 2ch 48000Hz, blk 11520 bytes (60ms) for playback
audio2: slinear_le:16 1ch 48000Hz, blk 6000 bytes (62.5ms) for recording
spkr3 at audio2: PC Speaker (synthesized)
wsbell at spkr3 not configured
uhidev1 at uhub5 port 1 configuration 1 interface 3
uhidev1: C-Media Electronics Inc. (0x0d8c) Genesis Radium 100 (0x0014), rev 1.10/1.00, addr 3, iclass 3/0
uhid1 at uhidev1: input=4, output=4, feature=0
uvideo0 at uhub5 port 2 configuration 1 interface 0: Generic (0x0bda) Streaming Webcam (0x5822), rev 2.10/22.08, addr 4
video0 at uvideo0pool redzone disabled for ‘video’
: Generic (0x0bda) Streaming Webcam (0x5822), rev 2.10/22.08, addr 4
uaudio1 at uhub5 port 2 configuration 1 interface 2
uaudio1: Generic (0x0bda) Streaming Webcam (0x5822), rev 2.10/22.08, addr 4
uaudio1: audio rev 1.00
uaudio1: 2 mixer controls
audio3 at uaudio1: capture
audio3: slinear_le:16 2ch 48000Hz, blk 12960 bytes (67.5ms) for recording
uhidev2 at uhub5 port 3 configuration 1 interface 0
uhidev2: SteelSeries (0x1038) SteelSeries Rival 110 Gaming Mouse (0x1729), rev 1.10/0.34, addr 5, iclass 3/0
uhid2 at uhidev2: input=32, output=32, feature=0
uhidev3 at uhub5 port 3 configuration 1 interface 1
uhidev3: SteelSeries (0x1038) SteelSeries Rival 110 Gaming Mouse (0x1729), rev 1.10/0.34, addr 5, iclass 3/1
ums0 at uhidev3: 6 buttons and Z dir
wsmouse0 at ums0 mux 0
uhidev4 at uhub5 port 4 configuration 1 interface 0
uhidev4: CHERRY (0x046a) CHERRY Keyboard (0x00e0), rev 2.00/1.02, addr 6, iclass 3/1
ukbd0 at uhidev4
wskbd0 at ukbd0: console keyboard, using wsdisplay0
uhidev5 at uhub5 port 4 configuration 1 interface 1
uhidev5: CHERRY (0x046a) CHERRY Keyboard (0x00e0), rev 2.00/1.02, addr 6, iclass 3/1
uhidev5: 5 report ids
ukbd1 at uhidev5 reportid 1
wskbd1 at ukbd1 mux 1
wskbd1: connecting to wsdisplay0
uhid3 at uhidev5 reportid 2: input=1, output=0, feature=0
uhid4 at uhidev5 reportid 3: input=2, output=0, feature=0
uhid5 at uhidev5 reportid 4: input=63, output=63, feature=0
ums1 at uhidev5 reportid 5: 5 buttons, W and Z dirs
wsmouse1 at ums1 mux 0
{drm:netbsd:amdgpu_vm_init+0x1a0} VM update mode is SDMA
{drm:netbsd:amdgpu_vm_init+0x1a0} VM update mode is SDMA
{drm:netbsd:amdgpu_vm_init+0x1a0} VM update mode is SDMA
{drm:netbsd:amdgpu_vm_init+0x1a0} VM update mode is SDMA
{drm:netbsd:amdgpu_vm_init+0x1a0} VM update mode is SDMA
{drm:netbsd:dce_v11_0_pageflip_irq+0xf2} amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)

NetBSD 9.3 released

The NetBSD project announced the third release from netbsd-9 branch on 4th of August, 2022. It includes security and stability fixes, as well as some selected feature enhancements. Main highlights can be found in release announcement, a complete list of changes from 9.2 release in CHANGES-9.3 file. The release can be downloaded from CDN service or any other project mirrors.

It is strongly recommended to update for users of earlier NetBSD releases.

com(4) and UEFI bootloader

NetBSD has an option to redirect console to the serial device in the boot(8) selector program and it works pretty well with the BIOS bootloader. After switching to interactive mode, one can simply type consdev com0 and console immediately switches to serial output (with default config of 9600 8N1). It is possible to change the speed by adding one after comma, for example, consdev com0,115200. Same command can be added to boot.cfg, if permanent serial output is required.

uefiboot, however, has some peculiarities. First of all, using device index doesn’t seem to work, thus specifying com0 or com1 doesn’t end up in serial output. The second issue is related to the fact that even if configuration is correct, console is not redirected immediately at boot selector application. Additionally, consdev command still reprints the banner in the screen contributing to more confusion and gives initial impression of broken functionality, especially if being used to BIOS bootloader functionality. I believe second issue is a bug, unless there are some technical limitations. Nevertheless, the console redirection to serial device still works right after the boot process starts, if serial device address is used instead of index in consdev command. Format is consdev com,addr,speed (please, take attention to no specific index while writing com). There are several ways to find the address of the serial device. I am usually retrieving it from dmesg(8) messages, for example dmesg |grep com0 should show something like com0 at acpi0 (UAR1, PNP0501-0): io 0x3f8-0x3ff irq 4 where 0x3f8 is the address required. This info quite often can be found in some BIOS options too. Typically com0 is a 0x3f8, thus consdev com,0x3f8,115200 command would properly redirect console to serial device as soon as boot starts.

It took me a bit of time to figure that out by reading documentation and some experimentation, later I also found the same recommendation in the mailing lists, but since UEFI boot is common these days, hopefully this info can save someones time and it is a good reminder for myself.